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| RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN PM73122 AAL1GATOR-32 REFERENCE DESIGN PRELIMINARY INFORMATION ISSUE 4: OCTOBER 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN PUBLIC REVISION HISTORY Issue No. 1 2 Issue Date Details of Change January 2000 November 2000 January 2001 October 2001 Document created. AAL1gator SRAMs changed in schematics due to part availability. Pull-downs added to SOC and CA signals of UTOPIA buses. Clarifications made to document. Byte Write Enable lines corrected (swapped) on AAL1gator-32 SRAMs in schematics. Added appendix D for DS3 Adaptive Clock Recovery VHDL source code, and changed document status from preliminary to released, to match production release of AAL1gator-32 device. 3 4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN CONTENTS 1 INTRODUCTION ......................................................................................1 1.1 1.2 1.3 2 3 4 PURPOSE .....................................................................................1 SCOPE ..........................................................................................1 APPLICATIONS .............................................................................1 FEATURES...............................................................................................2 GENERAL DESCRIPTION .......................................................................3 BLOCK DESCRIPTIONS..........................................................................5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 SPECTRA-155...............................................................................5 TEMUX ..........................................................................................6 AAL1GATOR-32.............................................................................6 S/UNI-APEX.................................................................................12 S/UNI-ATLAS ...............................................................................13 MICROPROCESSOR INTERFACE AND CPLD ..........................15 POWER SUPPLY ........................................................................16 5 6 7 8 9 10 11 12 TESTABILITY .........................................................................................18 IMPLEMENTATION DESCRIPTION.......................................................20 GLOSSARY ............................................................................................22 REFERENCES .......................................................................................23 DISCLAIMER..........................................................................................24 APPENDIX A: AAL1GATOR-32 REFERENCE DESIGN SCHEMATICS 25 APPENDIX B: U47 MICROPROCESSOR CPLD VHDL CODE..............26 APPENDIX C: EXTERNAL DS3 SRTS VHDL CODE .............................40 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 13 APPENDIX D: EXTERNAL DS3 ADAPTIVE CLOCK RECOVERY VHDL CODE .....................................................................................................49 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN LIST OF FIGURES FIGURE 1 AAL1GATOR-32 REFERENCE DESIGN .........................................3 FIGURE 2 SPECTRA-155 STS-3 CONFIGURATION........................................6 FIGURE 3 AAL1GATOR-32 CONFIGURATIONS ..............................................7 FIGURE 4 TEMUX- AAL1GATOR-32 SBI INTERFACE .....................................9 FIGURE 5 SRTS-BASED DS3/E3 CLOCK RECOVERY CIRCUIT..................12 FIGURE 6 MICROPROCESSOR INTERFACE BLOCK...................................16 FIGURE 7 SIMPLE SYSTEM TEST BENCH BLOCK DIAGRAM ....................18 FIGURE 8 COMPLEX SYSTEM TEST BENCH BLOCK DIAGRAM ................19 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 1 INTRODUCTION The AAL1gator-32 Circuit Emulation Service (CES) Reference Design provides a SONET/SDH network with T1, E1, E3 or DS3 access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. The AAL1gator-32 Reference Design is based on the 6U compact PCI standard. However, this reference design is a paper reference design only and has not been built or tested. 1.1 Purpose This document provides a detailed hardware specification for the AAL1gator-32 Reference Design. This specification is detailed enough to allow design implementation and verification. 1.2 Scope The purpose of this reference design is to assist engineers in designing their products using PMC-Sierra's PM73122 AAL1gator-32 and PM8315 TEMUX devices. A block diagram is shown for the design. A description is then given for the functional blocks of the design. A detailed implementation description then follows. 1.3 Applications * * * * * * * DACS with an ATM interface. Any Service, Any Port Application. ATM Access Multiplexers. Part of a TDM Digital Access Cross-connect Systems (DACS) Replacement. High density T1/E1 interfaces for multiplexers, multi-service switches, routers and digital modems. SONET/SDH Add Drop Multiplexers. SONET/SDH Terminal Multiplexers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 2 FEATURES * * * * Supports OC-3 capacity, scaleable to OC-12. Supports T1, E1, E3, and DS3 rates in channelized and unchannelized mode. Supports ATM and CES services. Telecom 8 bit Add/Drop TDM bus connects VT/TU channelized SONET/SDH processor (SPECTRA-155) to the high density framer (TEMUX) to support T1/E1 mapped payloads. Microprocessor interface utilized by a PCI bridge and a PCI connector. * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 3 GENERAL DESCRIPTION A block diagram of the design is shown in Figure 1 consisting of several blocks. The design is a single Compact PCI card using one PM5342 SPECTRA-155, three PM8315 TEMUXes, three PM73122 AAL1gator-32s, one PM7324 ATLAS, one PM7326 APEX, a PLX9054 PCI bridge, two CPLDs and a HFCT-5205 optical transceiver. Figure 1 AAL1gator-32 Reference Design PCI Connector CPLDs PCI Bridge Data &Address Bus SBI Telecom Bus ANY-PHY UTOPIA PM8315 TEMUX PM73122 AAL1gator -32 Connector UTOPIA LEVEL 2 UL1 OC3 PM5342 SPECTRA 155 PM8315 TEMUX PM73122 AAL1gator -32 PM7326 APEX UL2 UTOPIA LEVEL 2 PM7324 ATLAS PM8315 TEMUX PM73122 AAL1gator -32 A Hewlett Packard HFCT-5205 optical transceiver provides a SONET/SDH compliant link at a serial signal rate of 155.52 Mbit/s. The transceiver performs optical-to-electrical conversion, converting the OC-3 optical signal into an STS3/STM-1 stream and vice versa. This transceiver communicates with the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN PM5342 SPECTRA via a PECL interface. The SPECTRA extracts/aligns the SONET/SDH payload and acts as a Telecom Bus interface. The TEMUX devices receive/transmit data through the Telecom Bus and the data is then passed through the T1/E1 framers. It is then formatted for transmission to the AAL1gator-32 devices for CBR/VBR servicing. The APEX and ATLAS perform the routing, switching, traffic policing and shaping of the cells. The APEX and the ATLAS are connected to the AAL1gator-32 and the UTOPIA connector such that all cells first pass through the ATLAS so that policing and OAM functions can be performed first. The microprocessor interface, utilized by the PCI connector and bridge, configures, controls and monitors all the above devices. The CPLD in the design is used to generate a frame pulse signal for the SPECTRA-155, TEMUX, and AAL1gator-32 devices and to generate the chip select signals for the PMC-Sierra devices on the board. Power requirements of the board are +5V, +3.3V and 2.5V. The SPECTRA-155 requires 5V while the TEMUX, AAL1gator-32, and APEX devices require a +2.5V power supply. ATLAS requires +3.3V. SPECTRA-155, TEMUX, AAL1gator-32, and S/UNI-ATLAS devices require demultiplexed address and data bus for the microprocessor interfaces while S/UNIAPEX requires 32-bit multiplexed microprocessor bus. In order to provide maximum system implementation flexibility, a PCI bridge chip has been used. The two 80-pin female UTOPIA connectors carry the receive and transmit UTOPIA signals between the S/UNI-ATLAS and any external PHY board or a Parallel Cell Traffic Generator and Analyzer such as HP E1401B UTOPIA Tester. The design also includes several LED circuits for the device alarms and power indications. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 4 4.1 BLOCK DESCRIPTIONS SPECTRA-155 The SPECTRA-155 is a SONET/SDH payload extractor/aligner for use in STS-1, STS-3 or STS-3c interface applications, operating at serial interface speeds of up to 155 Mb/s. In the receive direction, the SPECTRA-155 receives SONET/SDH frames via a bit serial interface, recovers clock and data, and terminates the SONET/SDH regenerator section, multiplexer section and path overhead. It performs framing, descrambling, detects alarm conditions, and monitors section and line bit interleaved parity. In addition, the SPECTRA-155 interprets the received payload pointers and extracts the Synchronous Payload Envelope (SPE). The SPE extracted by SPECTRA-155 is placed on a Telecom DROP bus. The SPECTRA-155 maps the three DS3s from the STS-3 SPE and provides serialized bit streams with derived clocks. In the transmit direction, the SPECTRA-155 transmits SONET/SDH frames, via a bit serial interface, and formats the section, line and path overheads. It performs framing pattern insertion, scrambling, alarm signal insertion, and creates the section and line bit interleaved parity. In addition, the SPECTRA155 generates the transmit payload pointers. The inserted SPE is either sourced from a Telecom ADD bus stream, from DS3 serial streams, or from data streams. For the Telecom bus applications, the SPECTRA-155 maps the SPE from Telecom ADD bus into the transmit stream. Figure 2 shows the direct interface of the SPECTRA-155 to a Telecom bus. The SPECTRA-155 uses analog power pins QAVD, RAVD, and TAVD, which must be applied after VDD. A simple filtering network is placed on each of the analog pins to delay the voltage rise until the digital pins are at the proper voltage. For more information about the SPECTRA-155, please refer to [1]. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN Figure 2 SPECTRA-155 STS-3 Configuration SMODE[2:0]="000" ACK AC1J1V1 APL AD[7:0] ADP E/O O/E Telecombus Add Interface ODL PM5342 SPECTRA-155 DCK DC1J1V1 DPL DD[7:0] DDP Telecombus Drop Interface 4.2 TEMUX TEMUX is an integrated circuit which integrates 28 T1 framers, 21 E1 framers, SONET/SDH VT1.5/V2/TU-11/TU-12 bit asynchronous mapper and full featured M13 multiplexer with DS3 framer. It also contains a SONET/SDH DS3 mapper for terminating DS3 multiplexed T1 streams, SONET/SDH mapped T1 streams or SONET/SDH mapped E1 streams. Virtual Tributary VT1.5 carries enough bandwidth to transport a DS1 signal of 28 DS0s at 64 Kb/s. Analogously, VT2 carries enough bandwidth to transport an E1 (2.048 Mb/s) signal. The M13 multiplexing process involves the combination of 28 DS1 (1.544 Mb/s) signals into a single DS3 signal (44.736 Mb/s). The DS3 is asynchronously mapped into a STS-1 SPE. Three STS-1 signals form an STS-3. The device supports a byte serial Scalable Bandwidth Interconnect (SBI) bus interface for high density system side device interconnection of up to 84 T1 streams, 63 E1 streams, 3 DS3 streams or 3 E3 streams. On the line side TEMUX supports SONET/SDH Telecom bus and provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring. For more information about the TEMUX, please refer to [2] of the references. 4.3 AAL1gator-32 The purpose of the AAL1gator-32 is to provide high density T1/E1, or DS3/E3/J2 line interfaces access to an AAL1 CBR ATM network. The AAL1gator-32 can support 32 links via PMC-Sierra's SBI bus or eight 8Mb/s H-MVIP links. The PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN AAL1gator-32 is capable of supporting 1024 VCs. Figure 3 indicates the ways in which an AAL1gator-32 can be used to connect to T1/E1 or DS3/E3/J2 line interfaces. Figure 3 AAL1gator-32 Configurations UTOPIA AAL1gator-32 Structured or unstructured T1/E1 with CAS support MVIP TDM Switch 28 T1 Framers + M13 Mux + VT Mapper (TEMUX) SBI Unstructured DS3/E3/J2 T1/E1 Framer (TQUAD/EQUAD) T1/E1 Framer+LIU (COMET) DS3/E3/J2 Framer (S/UNI-QJET) T1/E1 LIU (QDSX) M13 Mux (D3MX) DS3 LIU (TUPP-PLUS) (SPECTRA-155) DS3/E3/J2 LIU In this design each AAL1gator-32 interfaces with a PM8315 TEMUX via the SBI bus to support: * * 28 structured/unstructured T1s if only 1 TEMUX is used, 32 if more than 1 TEMUX is used 21 structured/unstructured E1s if only 1 TEMUX is used, 32 if more than 1 TEMUX is used When used with the TEMUX, the AAL1gator-32 can be a part of a multiservice switch application which can provide circuit emulation services on E1 or T1 pipes being carried over a DS3 or OC-3 link. It can also provide circuit emulation services for an unstructured DS3 link. This system is scalable to an OC-12 system, using SPECTRA-622 instead of the SPECTRA-155 and more TEMUX and AAL1gator-32 devices. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN The AAL1 Segmentation and Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data, and the statistics. Some of the device's important functionality is as follows: * * * * * Compliant with the ATM Forum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), and the ITU-T I.363.1 Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with the ATM Forum's DBCES specification (AF-VTOA-0085). Supports idle channel detection via processor intervention, CAS signaling, or data pattern detection. Provides idle channel indication on a per channel basis. Provides AAL1 segmentation and reassembly of 16 individual E1 or T1 lines in the direct low speed mode, 8 H-MVIP lines at 8 Mb/s in the H-MVIP mode, or 2 E3 or DS3 lines in the high speed mode. Using the Scalable Bandwidth Interconnect (SBI) Interface, provides AAL1 segmentation and reassembly of up to 32 T1, E1, VT1.5, or VT2 links, or 2 DS3 or E3 links. Provides a standard UTOPIA level 2 Interface which optionally supports parity and runs up to 52 MHz. The following modes are supported: * * * * * 16-bit Level 2, Multi-Phy Mode (MPHY) 8-bit Level 2, MPHY 8-bit Level 1, ATM Master * * Supports up to 1024 Virtual Channels (VC). Supports n x 64 (consecutive channels) and m x 64 (non-consecutive channels) structured data format. Each AAL1gator-32 interfaces with a TEMUX through PMC-Sierra's SBI bus. The high level design of this interface is shown in Figure 4. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN Figure 4 2 kHz FP 19.44 MHz TEMUX- AAL1gator-32 SBI Interface DROP SREFCLK SC1FP SBI Interface ADD REFCLK C1FP C1FP SBI SBI Interfcae Interface TEMUX AAL1gator-32 SBIACT SBIDET0 SBIDET1 AACTIVE ADETECT SREFCLK SC1FP SBI TEMUX Interfcae SBIACT SBIDET0 SBIDET1 REFCLK REFCLK C1FP C1FP SBI Interface AAL1gator-32 AACTIVE ADETECT SREFCLK SC1FP SBI Interface REFCLK C1FP SBI Interface TEMUX AAL1gator-32 SBIACT SBIDET0 SBIDET1 AACTIVE ADETECT SBI BUS This reference design uses zero bus turnaround (ZBT) synchronous SRAM for the AAL1gator-32 so that the highest degree of performance is available. ZBT SSRAM should be used in situations where the AAL1gator-32 is configured for a large number of partial cell VCs or a large number of VCs are being used over all channels. For normal operation, pipelined single-cycle deselect SSRAM (nonZBT) will suffice. Note that the connections between the AAL1gator-32 and ZBT or non-ZBT SSRAM are slightly different. Refer to the AAL1gator-32 datasheet and the datasheet of the SSRAM being used for details. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN PMC-Sierra does not recommend the use of one specific manufacturer's SSRAM. A list of possible solutions is provided below; however, this list should not be considered exhaustive. Pipelined Single-Cycle Deselect SSRAM (non-ZBT) Motorola MCM69P819-4 (TQ4) Galvantech (Cypress) GVT71256G18-6 Micron MT58L25618P-10 GSI Technology GS84018T/B-100 Zero Bus Turnaround (ZBT) SSRAM Cypress CY71352 Micron MT55L256L18P-10 Motorola MCM63Z818-100 (TQ133) The AAL1gator-32 is capable of internally synthesizing an E1/T1 clock for each line using both the synchronous residual timestamp (SRTS) and adaptive clock recovery methods in unstructured data format (UDF-ML) mode. The AAL1gator32 is not able to internally synthesize a DS3/E3 line rate clock; however, the AAL1gator-32 does output both SRTS and adaptive clock recovery information to the Clock Generation and Control (CGC) port to support external DS3/E3 clock synthesis for two DS3/E3 signals. The CGC port of the AAL1gator-32 is connected to the CPLD so that a few different functions can be implement externally. These possible functions are: * * * * * External control of the AAL1gator-32 internal T1/E1 clock synthesizers to implement a custom SRTS algorithm. Generation of 32 external TL_CLK sources per AAL1gator-32 when in SBI mode. Read CGC nibbles for implementation of an external adaptive clocking algorithm. Read CGC nibbles for implementation of an external DS3/E3 SRTS clock recovery algorithm. Read CGC nibbles for implementation of an external DS3/E3 adaptive clock recovery algorithm. As the last two points suggest, the high speed SRTS information from the AAL1gator-32's SRTS port can be used to synthesize and control a DS3 or E3 clock externally. The circuitry for external DS3/E3 SRTS is shown in Figure 5. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN Some external algorithms use digital or analog filtering between certain stages of the circuitry; however, PMC-Sierra has found the circuitry of Figure 5 to synthesize and track the appropriate clock well and therefore PMC-Sierra does not recommend any other filtering. External SRTS is not implemented within this reference design. However, the Analog Devices AD7302 8-bit DAC and the MMD VCXO MVA3025HACY (DS3: 44.736 MHz, E3: 34.368 MHz) have been used with success. Similar devices are also available from other manufactures. The VHDL code for the CPLD is given in Appendix C. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN Figure 5 SRTS-based DS3/E3 Clock Recovery Circuit Network-Derived 77.76 MHz VCC NCLK CGC_DOUT CGC_LINE SRTS_STRB D0-D7 REF IN PM73122 AAL1gator-32 CPLD 8-bit DAC (AD7302) TL_CLK(0) VOUT to LIU VCXO This circuit functions as follows: the AAL1gator-32 asserts SRTS_STRB indicating a new SRTS nibble is available on CGC_DOUT for the line indicated by CGC_LINE. A lookup table within the CPLD is then used to convert the CGC_DOUT nibble into an 8-bit code to drive the digital-to-analog converter (DAC). The DAC output voltage then controls the voltage-controlled oscillator VCXO, which has a DS3 or E3 center frequency. The resulting clock is then fed to the AAL1gator-32 TL_CLK(0) input and the LIU. Note that NCLK must be network derived, but SYSCLK can be asynchronous to the network. The circuit shown in Figure 5 above can also be used for DS3/E3 adaptive clock recovery with the following changes: the network-derived 77.76 MHz clock is not used, and CGC output ADAP_STBH should be connected to the CPLD. A DS3 Adaptive Clock Recovery CPLD implementation is given in Appendix D. For a more detailed description of the AAL1gator-32, please refer to [3] of the references. 4.4 S/UNI-APEX The PM7326 S/UNI-APEX is a full duplex ATM traffic management device, providing cell switching, per VC queuing, traffic shaping, congestion PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN management, and hierarchical scheduling to up to 2048 loop ports and up to 4 WAN ports. The S/UNI APEX provides per-VC queuing for 64K VCs. A per-VC queue may be allocated to any Class of Service (COS), within any port, in either direction (ingress or egress path). Per-VC queuing enables PCR or SCR per-VC shaping on WAN ports and greater fairness of bandwidth allocation between VCs within a COS. The APEX supports an 8/16-bit Any-PHY compliant loop side master/slave interface supporting up to 2048 ports. Egress cell transfers across the interface are identified via an inband port identifier prepended to the cell. The slave devices must match the inband port identifier with their own port ID or port ID range in order to accept the cell. Per port egress flow control is effected via a 12bit address polling bus to which the appropriate slave device responds with out of band per port flow control status. Ingress cell transfers across the interface are effected via a combination of UTOPIA L2 flow control polling and device selection for up to 32 slave devices. The Any-PHY loop side interface may be reconfigured as a standard single port 16-bit Any-PHY or UTOPIA L2 compliant slave interface. 16-bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. The S/UNI APEX provides an 8/16-bit Any-PHY or UTOPIA L2 compliant WAN side master interface supporting up to 4 ports. The 16-bit prepends are optionally supported on both ingress and egress for cell flow identification enabling use with external address resolution devices, switch fabric interfaces, or other layer devices. The S/UNI APEX provides a 36-bit SSRAM interface for context storage supporting up to 4MB of context for up to 64kVCs and up to 256k cell buffer pointer storage. Context Memory protection is provided via 2 bits of parity over each 34-bit word. The S/UNI-APEX should be used if functions such as VC-based switching or traffic management are required within a design. Traffic management includes congestion management, class of service aware scheduling, and shaping. For more information about the S/UNI-APEX, please refer to [4] of the references. 4.5 S/UNI-ATLAS The PM7324 S/UNI-ATM Layer Solution (S/UNI-ATLAS, or simply ATLAS) is a PMC-Sierra standard product that implements the following ATM Layer functions: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN * * * * * * OAM processing according to ITU-T I.610 1995 and 1998 living list. Header Translation on full VPI/VCI address range. Prepend/Postpend tagging. Cell rate policing according to ITU-T I.371 using the Generic Cell Rate Algorithm. GFR Policing according to ATM Forum's Traffic Management 4.0 1998 living list. Per-PHY queuing to prevent head-of-line blocking. The ATLAS performs both ingress and egress functionality. The ingress side has a SCI-PHY level 2 interface at the input, and a SCI-PHY level 1 interface at the output. Cells coming into the ATLAS from a PHY are identified according to the PHY ID, VPI, and VCI. The cells are processed according to the information stored in context RAM for the particular connection. Cells may also be copied to the microprocessor cell interface for external processing. The egress has a SCIPHY level 2 interface at both the input and output interface. The connection is identified according to the PHY ID, VPI, and VCI, and processed according to the information in external RAM for the particular connection. As with the ingress, cells can be copied to the microprocessor cell interface for external processing. The ATLAS is configured and controlled through a generic 16 bit asynchronous microprocessor bus. The S/UNI-ATLAS should be used in applications where policing or I.610 OAM compliance are required, or when traffic is destined for an ATM WAN or switch. Policing of ingress traffic is performed to ensure that the actual traffic pattern fits within contract (possibly for DBCES applications). Per VC counters are also available within the S/UNI-ATLAS for monitoring bandwidth. The S/UNI-ATLAS is utilized such that all ingress cells pass first through the S/UNI-ATLAS, then through the S/UNI-APEX, and then back out through the S/UNI-ATLAS again. This setup allows ingress packets to be policed at the ingress to the network, and for OAM cells to be looped back for I.610 compliance. For more detail on traffic management and switching, please refer to [5] of the references. For a more detailed description of the S/UNI-ATLAS, please refer to [6] of the references. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 4.6 Microprocessor Interface and CPLD As illustrated in Figure 6, the microprocessor interface to the card is implemented using the CompactPCI standards with a cPCI connector, a PCI 9054 chip and a CPLD. This interface provides an external host CPU connection to perform the following functions on the AAL1gator-32 Reference Design: * * * * Configuration of the SPECTRA-155, TEMUX, AAL1gator-32, S/UNI-APEX, and S/UNI-ATLAS devices Setting up connections in the AAL1gator-32, S/UNI-APEX, and S/UNI-ATLAS context RAMs Monitoring of alarms and interrupts in the SPECTRA-155, TEMUX, AAL1gator-32, S/UNI-APEX, and S/UNI-ATLAS devices Background Debug mode for the board's feature tests. Note that a second CPLD is included in the design for clocking; however, VHDL code is not included for this CPLD for external clocking options because the AAL1gator-32 is capable of performing these functions internally. Only users wishing to implement their own algorithm externally need to implement this CPLD. The essential characteristic of the PCI concept is the strict decoupling of an external processor's main memory subsystems and the standard expansion bus by means of a bridge. The PLX's PCI 9054 bridge is the PCI v2.2 compliant 32bit, 33 MHz bus master interface controller which enables PCI burst transfers up to 132 Mbytes per second. Since the S/UNI-APEX requires a multiplexed address/data bus, the PCI 9054 is configured for the multiplexed bus mode (J mode) on its local bus side. As shown in Figure 6, the 32-bit multiplexed AD[31:0] Address/Data bus from the PCI 9054 is directly connected to the APEX address/data pins. The remaining devices, by means of their Address Latch Enable (ALE) pins, have the microprocessor interface option to work with the multiplexed address/data bus. The ALE pin latches the address signals during the address phase of the bus transaction. Therefore, except for the APEX, the AD[31:0] is connected to the data port of the other devices. The proper resistive termination along the bus line is necessary to help with signal integrity. The additional A[28:2] address bus is connected to the other devices which need separate address lines through the CPLD. Also, the CPLD is used to generate the chip select and other microprocessor control signals for the PMC devices. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN Figure 6 Microprocessor Interface Block Serial EEPROM AD[31:0] Serial EEPROM Interface AD[31:0] UP Control AD[27:0] CS_0 APEX PCI_AD [31:0] A[28:2] A[28:2] CS [8:0] A[11:0] D[15:0] A[19:0] UP Control CS_1 UP Control cPCI PCI 9054 CPLD PCI _Control Control Signals Control ATLAS A[19:0] D[15:0] AAL1gator32 UP Control CS_2 TEMUX TEMUX A[13:0] D[7:0] TEMUX UP Control CS_5 TEMUX TEMUX A[9:0] D[7:0] SPECTRA-155 UP Control CS_8 4.7 Power Supply Power is provided to the AAL1gator-32 Reference Design through the Compact PCI interface. PMC-Sierra's devices require that the +3.3V power rail be higher voltage than the +2.5V power rail at all times. This is achieved by regulating the lower voltage from the higher voltage, as shown on page 29 of the schematics in the appendix. +5.0V and +3.3V are taken from the Compact PCI interface. +2.5V is then regulated using the LT1580 regulator. This regulator is designed to have a low dropout voltage, and therefore requires +5.0V as well. However, most of the current is drawn from the +3.3V rail. A zener diode is added to the +5.0V rail to PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN dampen any voltage spikes and LEDs are connected across each of the supply rails to indicate the presence of voltage. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 5 TESTABILITY Figure 7 illustrates a simple test bench connection for the AAL1gator-32 Reference Design Card. The required tester/analyzer for testing the reference design card must be capable of embedding ATM cells inside T1 or E1 frames, inside a DS3 or E3 bit stream, and inside a Synchronous Payload Envelope (SPE). The HP 37717C communications performance analyzer equipped with the optical interfaces, the optical adaptor, the SONET/SDH test and interfaces, the PDH/DSn and ATM test and interfaces, and the ATM services layer test options may be used for this purpose. The analyzer sources the STS-3 data in to the receiver and receives the returned data from the transmitter part of the optical data link module of the reference design card. Figure 7 Simple System Test Bench Block Diagram Development/Debug PC PCI Interface HP 37717C Analyzer RX TX TX AAL1gator-32 Reference Design Card ODL RX UTOPIA Interface Figure 8 illustrates a complex test bench connection for the AAL1gator-32 Reference Design Card. The optical transceiver is attached to external SONET test equipment which sources OC3 data into the receiver and receives the returned data from the transmitter part of the optical data link module of the card. A Cell Traffic Generator and Analyzer such as HP E14011B receives/transmits and monitors the ATM cell traffic from/to the reference design card through the UTOPIA connector on the board. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN Figure 8 Complex System Test Bench Block Diagram Development/Debug PC PCI Interface SONET Tester RX TX TX AAL1gator-32 Reference Design Card ODL RX UTOPIA Interface Cell Traffic Generator & Analyzer (HP E1401B) UTOPIA Port The diagnostic loopback mode of the devices can be used to loopback the transmit data to the receive path. The cPCI port of the Reference Design Card allows the microprocessor interface with a host CPU (the development/debug PC) to monitor the status of SPECTRA-155, TEMUX, AAL1gator-32, S/UNI-APEX, and S/UNI-ATLAS devices. This port is also used to program registers for initialization, software load and reset, and diagnostics. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 6 IMPLEMENTATION DESCRIPTION The schematic contains 29 pages as follows: Sheet 1: Root Drawing This sheet provides a block view of the interface signals between each block of the AAL1gator-32 Reference Design. Sheet 2: Optical Interface This sheet shows the connections needed for the HP HFCT5205 optical transceiver. Sheet 3: SPECTRA-155 This sheet contains the PM5342 SPECTRA-155, alarm LEDs, and other supporting circuitry. Sheet 4-9: Temuxes Block These sheets contain the 3 PM8315 TEMUXes and their connections. Sheet 10-18: AAL1gator-32 Block These sheets contain the 3 PM73122 AAL1gator-32s including their synchronous SRAMs. Sheet 19-21: Apex Block These sheets contain the PM7326 APEX and the requied synchronous DRAM and SRAM. Sheet 22-23: Atlas Block These sheets contain the PM7324 ATLAS and the the required synchronous SRAM. Sheet 24: UTOPIA Connector This sheet contains the transmit and receive UTOPIA Level 2 connector. Sheet 25: 25 MHz Oscillator Block This sheet contains the 25 MHz crystal oscillator for the UTOPIA buses. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN Sheet 26-28: CPLD Block These sheets contain the two CPLDs that are used to generate frame pulses and distribute clock signals. Sheet 29: Power and Reset Block This sheet contains the voltage regulators for powering the devices. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 7 GLOSSARY AAL1 ASAP ATM CBR CES COS PCI SAR SCI-PHY SBI SRTS UTOPIA VBR VC VCC VCI VP VPC VPI WAN ZBT ATM Adaptation Layer 1 Any Service-Any Port Asynchronous Transfer Mode Constant Bit Rate Circuit Emulation Services Class of Service Peripheral Component Interconnect Segmentation and Re-assembly PMC-Sierra enhanced UTOPIA bus Scalable Bandwidth Interconnect Synchronous Residual Time Stamp Universal Test & Operations PHY Interface for ATM Variable Bit Rate Virtual Circuit Virtual Channel Connection Virtual Circuit Identifier Virtual Path Virtual Path Connection Virtual Path Identifier Wide Area Network Zero Bus Turnaround PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 8 REFERENCES 1. PMC-Sierra Inc., PMC-970133, "SONET/SDH Payload Extractor/Aligner for 155 Mbits/s Telecom Standard Product Data Sheet", August 1998, Issue 4. 2. PMC-Sierra Inc., PMC-981125, "High Density T1/E1 Framer With Integrated VT/TU Mapper and M13 Multiplexer Telecom Standard Product Data Sheet", June 1998, Issue 4. 3. PMC-Sierra Inc., PMC-981419, "ATM Adaptation Layer 1 Segmentation and Reassembly Processor-32 (AAL1gator-32) Telecom Standard Product Data Sheet", December 1998, Issue 1. 4. PMC-Sierra Inc., PMC-981224, "ATM/Packet Traffic Manager and Switch (S/UNI-APEX) Data Sheet", Issue 3. 5. PMC-Sierra, Inc., PMC-1981024, "Traffic Management and Switching Using the Vortex Chipset: S/UNI-APEX Technical Overview", August 30, 1999, Issue 1.0. 6. PMC-Sierra Inc., PMC-971154, "S/UNI-ATM Layer Solution Data Sheet", January 1999, Issue 5. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 9 DISCLAIMER This document is a paper reference design and, as such, has not been built or tested. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 10 APPENDIX A: AAL1GATOR-32 REFERENCE DESIGN SCHEMATICS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H PAGE 25 25MHZ_OSCILLATOR_BLOCK PAGES 10-18 AAL1GATOR_32_BLOCK RPHY_CLK PAGE 3 SPECTRA_155_BLOCK TELECOM_AC1J1V1 TELECOM_AD<7..0> G TELECOM_ADP TELECOM_APL PAGE 2 OPTICAL_INTERFACE RXDP RXDN SD TXDP TXDN TELECOM_DC1J1V1 TELECOM_DD<7..0> TELECOM_DDP TELECOM_DPL RXDP RXDN SD TXDP F TXDN RXDP RXDN SD XCLK TXDP TXDN SS1_DFP SS0_DCK RRCLK TRCLK SS13_ACK CICLK<2..0> SPECTRA_UP_CONTROL<4..0> CECLK<2..0> CTCLK<1..0> RECVCLK1 L_AD<31..0> E TEMUX_UP_CONTROL<10..0> CHIP_ADDRESS<19..0> CHIP_ADDRESS<19..0> JTAG<2..0> TDO13 TDO1 JTAG<2..0> TDO1 TDO4 L_AD<31..0> SREFCLK SREFCLK TELECOM_AC1J1V1 TELECOM_AD<7..0> TELECOM_ADP TELECOM_APL TELECOM_DC1J1V1 TELECOM_DD<7..0> TELECOM_DDP TELECOM_DPL PAGES 4-9 TEMUXES_BLOCK TELECOM_AC1J1V1 TELECOM_AD<7..0> SBI_AV5 SBI_AD<7..0> TELECOM_ADP SBI_ADP TELECOM_APL TELECOM_DC1J1V1 TELECOM_DD<7..0> TELECOM_DDP TELECOM_DPL LAC1 CLK52M LREFCLK XCLK ADJUST SBI_APL SBI_DV5 SBI_DD<7..0> SBI_DDP SBI_DPL C1FP ADJUST SBI_AV5 SBI_AD<7..0> SBI_ADP SBI_APL SBI_DV5 SBI_DD<7..0> SBI_DDP SBI_DPL SBI_AV5 SBI_AD<7..0> SBI_ADP SBI_APL SBI_DV5 SBI_DD<7..0> SBI_DDP SBI_DPL C1FP ADJUST ANYPHY_TDAT<15..0> ANYPHY_TADR<3..0> ANYPHY_TENB SREFCLK ANYPHY_TPA ANYPHY_TPAR AAL_UP_CONTROL<13..0> ANYPHY_TSX L_AD<31..0> FASTCLK AACTIVE<3..1> ADETECT<3..1> TL_CLK<95..0> RL_CLK<5..0> CHIP_ADDRESS<19..0> CGC_VALID<2..0> CGC_SER_D<2..0> CGC_DOUT<11..0> CGC_LINES<14..0> SRTS_STRB<2..0> ADAP_STRB<2..0> RSTB TDAT<15..0> TDAT<15..0> TADR<4..0> TADR<4..0> TPRTY TWRENB TCA TSOC BCLK LTCLK LRCLK WRDAT<15..0> WRPRTY WRENB WRPA WRSOP WRDAT<15..0> RDAT<15..0> WRPRTY RADR<4..0> WRENB RPRTY WRPA RRDENB WRSOP RCA RSOC OFCLK RFCLK WTDAT<15..0> WTADR<2..0> WTPRTY WTENB TDAT<15..0> WTPA TADR<4..0> WTSOP TPRTY TWRENB TCA TSOC ATLAS_UP_CONTROL<5..0> L_AD<31..0> CHIP_ADDRESS<19..0> JTAG<2..0> TDO10 TDO12 JTAG<2..0> TDO12 TDO13 TPHY_CLK RPHY_CLK TPHY_CLK LRCLK LTCLK BCLK RDAT<15..0> RADR<4..0> RFCLK OFCLK LCLK_CPLD LCLK WRCLK H RDAT<15..0> RADR<4..0> RPRTY RDENB RCA RSOC G PAGES 19-21 APEX_BLOCK PAGES 22-23 ATLAS_BLOCK ANYPHY_TDAT<15..0> ANYPHY_TDAT<15..0> WRCLK ANYPHY_TADR<3..0> ANYPHY_TADR<3..0> ANYPHY_TENB WTDAT<15..0> ANYPHY_TPA WTADR<2..0> ANYPHY_TPAR WTPRTY ANYPHY_TSX WTENB WTPA WTSOP APEX_UP_CONTROL<10..0> F E NCLK<2..0> AAL_SYSCLK JTAG<2..0> TDO4 TDO10 RSTB L_AD<31..0> RSTB RSTB JTAG<2..0> D CHIP_ADDRESS<19..0> L_AD<31..0> PAGES 26-27 CPLD_BLOCK AAL_UP_CONTROL<13..0> TEMUX_UP_CONTROL<10..0> SREFCLK RECVCLK1 C1FP CTCLK<1..0> CTCLK<1..0> FASTCLK CECLK<2..0> CECLK<2..0> CICLK<2..0> CICLK<2..0> AACTIVE<3..1> ADETECT<3..1> RSTB D PAGE 24 UTOPIA_CONNECTOR TDAT<15..0> TADR<4..0> TPRTY TWRENB TCA TSOC PAGE 28 CPCI_PCI9054_BLOCK LCLK PAGE 29 POWER RSTB PCI_VCC PCI_3_3V RDAT<15..0> RADR<4..0> RPRTY RRDENB RCA RSOC C TL_CLK<95..0> RL_CLK<5..0> CGC_VALID<2..0> CGC_SER<2..0> CGC_SER_D<2..0> CGC_DOUT<11..0> CGC_DOUT<11..0> CGC_LINES<14..0> CGC_LINES<14..0> SRTS_STRB<2..0> ADAP_STRB<2..0> NCLK<2..0> AAL_SYSCLK SRTS_STRB<2..0> ADAP_STRB<2..0> NCLK<2..0> C APEX_UP_CONTROL<10..0> B XCLK ATLAS_UP_CONTROL<5..0> LREFCLK CLK52M LA<28..2> LAC1 SS1_DFP SS0_DCK RRCLK TRCLK SS13_ACK SPECTRA_UP_CONTROL<4..0> A CHIP_ADDRESS<19..0> LBE<1..0> UP_CONTROL<8..0> L_INTB L_BTERMB L_AD<31..0> APEX_UP_CONTROL<10..0> PCI_VCC ATLAS_UP_CONTROL<5..0> PCI_3_3V LA<28..2> LBE<1..0> UP_CONTROL<8..0> LA<28..2> LBE<1..0> UP_CONTROL<8..0> L_INTB L_BTERMB L_AD<31..0> B PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: DRAWING TITLE=ASAP_CES_ROOT ABBREV=ASAP_CES_ROOT LAST_MODIFIED=Thu Nov 22 14:26:10 2001 TITLE: AAL1GATOR-32 CES REF DESIGN ROOT DRAWING ENGINEER: 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:1 TRUE 1 OF 29 A SPECTRA_UP_CONTROL<4..0> CHIP_ADDRESS<19..0> RSTB LCLK_CPLD 10 9 8 7 6 5 4 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H NOTE: VCC IS +5V DC. H G VCC 2.7 R44 C67 C68 0.01UF 0.1UF 22UF C69 G VCC 2.7 6 R45 5 RN166 RN166 RN166 RN166 1 2 3 4 RES_ARRAY_4 8 7 6 5 330 330 330 330 F 0.1UF 0.01UF 22UF C70 C71 C72 AC U1 TX_VCC 9 F RX_VCC 1 SD RXDP RXDN 4 2 3 SD\I RXDP\I RXDN\I 3D1< 3D1< 3D1< 50 OHM LINES HFCT5205 VEET VEER TXDP TXDN 8 7 TXDP\I TXDN\I 3C1> 3C1> 50 OHM LINES 49.9 49.9 R46 R47 237 E E 0.01UF 681 R49 C73 D R48 D C C B DRAWING: OPTICAL_BLOCK OPTICAL_BLOCK Thu Nov 22 15:06:04 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN OPTICAL INTERFACE ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:2 1 OF 29 A 10 0.01UF C30 0.01UF C29 0.01UF C28 0.01UF C27 0.01UF C26 0.01UF C25 0.01UF C24 0.01UF 0.01UF 9 C22 0.01UF C21 0.01UF C20 0.01UF C19 0.01UF C18 0.01UF C17 0.01UF 8 C16 0.01UF C15 0.01UF C14 0.01UF C13 0.01UF C12 0.01UF C11 0.01UF 7 C10 0.01UF C9 0.01UF C8 0.01UF C7 0.01UF C6 0.01UF C5 0.01UF 6 C4 0.01UF C3 0.01UF C2 0.01UF 5 4 3 2 1 VCC REVISIONS C1 C23 ZONE SALM LOF LOS LAIS LRDI RALM1 RALM2 RALM3 RED D5 1 2 2 2 2 REV DESCRIPTION DATE APPR VCC 1 2 3 4 1 2 3 4 RES_ARRAY_4 H 2.7 4.7UF 0.1UF 1 C45 0.1UF 0.01UF 4.7UF C42 R4 C38 0.01UF 2.7 R8 1 2.7 C55 0.01UF 4.7UF 0.1UF R1 1 D6 D8 D11 D12 1 1 1 1 2 2 2 2 RED D7 RED D9 RED D10 RED 1 1 1 C48 C31 C34 RN28 RN28 RED RN28 RN28 RED RN29 RN29 RED RN29 RN29 8 7 6 5 8 7 6 5 270 270 270 270 270 270 270 270 H C58 C52 SPECTRA-155 ALARMS LEDS 11 12 13 14 15 16 17 2.7 4.7UF 2.7 4.7UF C49 0.1UF 0.1UF R2 2 0.01UF C39 C56 0.01UF 18 2 U50 OE2 OE1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 2 0.01UF 4.7UF C46 0.1UF C43 C32 C35 R9 C53 2.7 HCT540 C59 Y0 R5 19 1 A7 A6 A5 A4 A3 A2 A1 3 G 2.7 2.7 C60 0.1UF C57 0.01UF 3 0.01UF 4.7UF 0.1UF C50 C40 4.7UF 2.7 3 R6 R3 9 8 7 6 5 4 2 A0 3 TAVD<3..1> G 1 2 C54 RALM<3..1> VCC RAVD<4..1> N18 M17 P20 U20 U19 L20 L17 F17 C36 C44 0.01UF 4.7UF C47 0.1UF R10 3 C33 TP4 T TP5 R19 R18 T18 T19 2.7 4.7UF 0.1UF R7 0.01UF 4 QAVD<3..1> NC/POWER<2..1> QAVD<3..1> RAVD<4..1> VDD<29..0> TAVD<3..1> J8 JTAG PORT P_1 P_2 P_3 P_4 P_5 P_6 T U2 C41 LOS/RRCPFP LAIS/RRCPDAT LRDI/RRCPCLK RALM<3..1> C51 C37 SALM LOF F 1 2 3 4 5 6 D19 D20 E17 D18 E18 TCK TMS TDI TDO TRSTB RLOW RSUC RSOW ROWCLK RCLK RXC RAD RFP M20 F B3E<3..1> RSLDCLK RSLD RLDCLK RLD ROHCLK ROH T20 R17 N17 R20 P19 P18 U18 V17 T17 1 2 3 D16 0 1 2 TRIS_OHB 23E10> 5E9< 17E6< 14D5< 11E5< 9E9< 7E9< 5E9< 23B2< 21D6< 20H4< 20E4< TDO13\I TDO1\I JTAG<2..0>\I BYTE TELECOM MODE SS0_DCK\I SS1_DFP\I TELECOM_DD<7..0>\I RN126 RN126 RN126 RN126 RN126 RN126 RN126 RN126 RN127 RN127 RN127 RN127 RN127 RN127 RN127 RN127 RN128 RN128 RN128 RN128 RN128 RN128 RN128 RN128 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 R13 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 B17 A17 C16 SMODE0 SMODE1 SMODE2 SS0 SS1 SS2 SS3 SS4 SS5 SS6 SS7 SS8 SS9 SS10 SS11 SS12 SS13 SS14 SS15 SS16 SS17 SS18 SS19 SS20 SS21 SS22 SS23 SS24 SS25 SS26 SS27 SS28 SS29 SS30 SS31 SS32 SS33 SS34 RTOHCLK RTOH RTOHFP RPOHCLK<3..1> RPOH<3..1> RPOHFP<3..1> RTCEN<3..1> RTCOH<3..1> C1 C2 RRCLK+ RRCLK- E 28E3> 28F3> 9F9<7F9< 5F9< 0 1 2 3 4 5 6 7 9F9< 7F9<5F9< 9F9< 7F9< 5F9< 9F9< 7F9<5F9< 28E3> 8F9> 6F9> 4F9> TELECOM_DPL\I TELECOM_DC1J1V1\I TELECOM_DDP\I SS13_ACK\I TELECOM_AD<7..0>\I D 8F9> 6E9> 4F9> 4F9> 8F9> 6E9> 4F9> 0 1 2 3 4 5 6 7 TELECOM_APL\I TELECOM_AC1J1V1\I TELECOM_ADP\I 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 VCC 4.7K R29 D15 B16 A16 C15 B15 A15 C14 D13 B14 A14 C13 D12 B13 C12 B12 A12 D11 C11 B11 A11 C10 B10 B9 C9 A8 D9 B8 C8 A7 B7 D8 C7 A6 B6 C6 RN33 RN33 RN33 RN33 RN34 RN34 1 2 3 4 1 2 8 7 6 5 8 7 330 330 330 330 330 330 E RTCEN<3..1> RTCOH<3..1> W16 Y16 Y14 W14 0.1UF C66 1 2 3 R4375 C65 0.01UF R42 RRCLK\I RXDP\I 28D9> 2F4> PM5342 RXD+ RXD- 100 SPECTRA W12 W11 ALOS+ ALOS- C64 0.01UF V12 C63 0.01UF U12 RXDN\I SD\I 2F4> 2F4> D TRCLK+ TRCLK- W9 Y9 75 R41 C610.01UF R40237 R39237 TRCLK\I TXDP\I TXDN\I 28D9> 2F4< 2F4< VCC C 2 1 4 3 TXD+ TXDG2 F2 F3 F1 G3 E19 H4 9 8 <7..0> K2 K3 W5 Y5 C620.01UF 22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 4D9<> 8D9< 6C9< 29B5<> 28B3<> 26C5> 28E9<> RSTB\I SPECTRA_UP_CONTROL<4..0>\I 0 MBEB CSB ALE WRB/RWB RDB/E RSTB INTB A9 A8 A<7..0> VSS<28..0> NC_GNDA<4..1> TLRDI/TRCPFP TLAIS/TRCPDAT RLAIS/TRCPCLK D<7..0> QAVS<2..1> RAVS<4..1> TAVS<3..1> NCP<5..1> TPOHCLK<3..1> TPOH<3..1> TPOHFP<3..1> TPOHEN<3..1> TTOHCLK TTOH TTOHFP TTOHEN TOHCLK TOH TLDCLK TLD TSLDCLK TSLD TFP TCLK TACK TXC TAD TAFP TPOH<3..1> TPOHEN<3..1> T3 W4 P2 U5 T1 T2 U1 R4 R3 R2 N3 C 28F3> 17F5<> 14F5<> 11F5<> 8D9<> 6D9<> 4D9<> 28C3<> 25G3<> 22C4<> 21D10<> CHIP_ADDRESS<19..0>\I L_AD<31..0>\I <7..0> F4 E1 A5 B5 VCC RN27 RN27 RN27 RN27 1 2 3 4 RES_ARRAY_4 TLOW TSUC TSOW TOWCLK B SCPI0 SCPI1 SCPO0 SCPO1 TP3 T DRAWING: SPECTRA_BLOCK SPECTRA_155 Thu Nov 22 15:05:21 2001 B TATP RATP 8 7 6 5 4.7K 4.7K 4.7K 4.7K RBYP TBYP 1 2 3 1 2 3 A RN23 RN23 RN30 RN30 RN30 RN30 RN31 RN31 RN31 RN31 RN32 RN32 RN32 RN32 3 4 1 2 3 4 1 2 3 4 1 2 3 4 6 5 8 7 6 5 8 7 6 5 8 7 6 5 330 330 330 330 330 330 330 330 330 330 330 330 330 330 U16 W6 U3 U2 T4 V4 U6 Y6 U8 Y4 P3 N4 R1 W17 Y17 TP1 T P1 TP2 T PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN SPECTRA-155 ENGINEER: BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:3 1 OF 29 A 10 9 8 7 6 5 4 3 10 3.3 V 0.01UF C85 0.01UF C83 0.01UF C82 0.01UF C81 0.01UF 9 8 2.5 V 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR C77 0.01UF C76 0.01UF C75 0.01UF C80 0.01UF C84 0.01UF C79 0.01UF 0.01UF C78 C74 H H G RN34 RN34 RN38 RN38 3 4 1 2 6 5 8 7 330 330 330 330 G 3.3 V AA12 AA15 L21 C12 AA8 R21 H21 A15 2.5 V RN48 RN48 RN48 RN48 RN49 RN49 RN49 RN49 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 CICLK<0>\I 3.3 V 10K 10K 10K 10K 10K 10K 10K 10K CECLK<0>\I SBI_AD<7..0>\I C5 A4 L2 L1 B5 A5 E22 C20 B6 D4 M1 P2 C7 D6 M22 N19 B4 A3 R4 T2 A2 A7 N22 N21 N20 P19 AA3 AB4 F2 E4 K4 L3 D20 B22 U22 T20 F1 D3 R1 U4 C21 D21 V19 U21 G3 G2 T1 AB1 T22 T21 V22 AB22 AA21 Y19 Y4 AB3 7 6 29C4> N2 J2 R2 28F3> LREFCLK\I U3 VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDD2V5<8> VDD2V5<7> VDD2V5<6> VDD2V5<5> VDD2V5<4> VDD2V5<3> VDD2V5<2> VDD2V5<1> C9 CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1> P1 N1 P4 M3 N4 M2 3D10< 8F9> 6F9> TELECOM_AD<7..0>\I 7 6 5 4 3 2 1 0 F RN35 RN35 RN35 RN35 RN36 RN36 RN36 RN36 RN37 RN37 RN37 1 2 3 4 1 2 3 4 1 2 3 8 7 6 5 8 7 6 5 8 7 6 22 22 22 22 22 22 22 22 22 22 22 28F3> 3D10< 3D10<8F9> 6E9> 3D10<8F9> 6E9> LAC1\I TELECOM_AC1J1V1\I TELECOM_ADP\I TELECOM_APL\I 3.3 V 4.7K R30 W12 AB10 AA10 Y10 W9 AB9 W8 W7 AB8 W13 AA11 W10 Y11 AB11 AB7 W6 AA6 AA7 A16 D16 B16 C15 D17 LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB CSB RDB WRB ALE D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB 29C4> 10G9> 13G9> 16G9> F RN50 RN50 5 4 1 2 3 4 1 2 8 7 6 5 8 7 330 330 330 330 330 330 RN50 RN50 3 2 RN51 RN51 RN38 RN38 RN39 RN39 RN39 RN39 RN40 RN40 RN40 RN40 RN41 RN41 RN41 RN41 RN42 RN42 RN42 RN42 RN43 RN43 RN43 RN43 RN44 RN44 RN44 RN44 RN45 RN45 RN45 RN45 RN46 RN46 RN46 RN46 RN47 RN47 RN47 RN47 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 0 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 TE1_INTB TE1_CSB TE_RDB TE_WRB TE1_ALE 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E 28D3<> 8E9<> 6E9<> 330 330 SBI_APL\I SBI_AV5\I 330 330 SBI_ADP\I TEMUX3_SBIACT 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 10E9> 13E9> 16E9> 10F9> 13F9> 16F9> 10F9> 13F9> 16F9> 9F3> TEMUX_UP_CONTROL<10..0>\I 3 7 6 0 E 22C4<> 21D10<> 17F5<> 14F5<> 11F5<> 8D9<> 6D9<> 3B10<> 28C3<> 25G3<> L_AD<31..0>\I D13 A13 B13 C13 D14 A14 B14 C14 B21 C19 A21 B20 B19 C18 A20 A19 A18 B17 D19 D18 C16 A17 A22 TEMUX PM8315 1 OF 2 D D UNUSED INPUTS 28F3> 29B5<> 28B3<> 26C5> 22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 3C10<> 8D9< 6C9< CHIP_ADDRESS<19..0>\I RSTB\I C VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> C L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12 P11 P10 P9 N3 Y12 L20 B12 J3 R3 Y8 Y15 R20 H20 B15 B9 B DRAWING: TEMUX_1.1 TMX1 Thu Nov 22 15:05:25 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN TEMUX-1.1 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:4 1 OF 29 A 10 3.3 V 0.01UF C98 0.01UF C97 0.01UF C96 0.01UF C95 0.01UF C94 0.01UF C93 0.01UF C92 0.01UF C91 0.01UF C90 0.01UF 9 8 7 6 5 4 3 2 1 REVISIONS C89 0.01UF C88 0.01UF C87 0.01UF ZONE C86 REV DESCRIPTION DATE APPR H H G G 3.3 V AA14 AA9 Y18 U20 M21 F20 C17 PBGA U3 28E3> B11 F3 M4 U3 Y5 VDD3V3<9> VDD3V3<8> VDD3V3<7> VDD3V3<6> VDD3V3<5> VDD3V3<4> VDD3V3<3> VDD3V3<2> VDD3V3<13> VDD3V3<12> VDD3V3<11> 3E10> TELECOM_DD<7..0>\I 7 6 5 4 3 2 1 0 P3 W17 AB15 W16 W15 AB14 W14 Y13 AA13 Y16 AB16 AA16 AB17 AB12 AB13 AA17 AB18 W18 AA18 AB19 W19 W5 Y7 AB6 E20 0 1 2 C3 C2 C4 B3 B1 VDD3V3<10> VDD3V3<1> CLK52M\I CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TCK TMS TDI TDO TRSTB D5 CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1> T4 B7 A6 D7 A8 C8 C10 B10 H4 J1 A10 D10 L19 M19 A11 D11 V4 U2 D12 A12 P22 P21 H2 G4 W2 Y2 G21 G22 P20 R19 T19 AA20 Y6 AA5 D2 E3 J4 K3 F21 E19 G19 H19 C1 D1 U1 T3 G20 F22 K19 L22 H1 H3 AA1 W3 F19 H22 Y20 W22 AB21 AB20 AB2 Y3 F RN57 RN57 RN58 RN58 RN58 RN58 RN59 RN59 RN59 RN59 3 4 1 2 3 4 1 2 3 4 RES_ARRAY_4 6 5 8 7 6 5 8 7 6 5 22 22 22 22 22 22 22 22 22 22 7 6 5 4 3 2 1 0 SREFCLK\I C1FP\I ADJUST\I TEMUX1_SBIACT TEMUX2_SBIACT SBI_DD<7..0>\I 28F3> 28F3> 7F3<> 9F3> 10F3< 13F4< 16F4< 6E2< 8E2< 7F3> 7F3> 9F3> 10F3<13F4<16F4< F 3D10> 3D10> 3E10> TELECOM_DC1J1V1\I TELECOM_DDP\I TELECOM_DPL\I RN51 RN51 RN52 RN52 RN52 RN52 RN53 RN53 RN53 3 4 1 2 3 4 1 2 3 4 1 2 6 5 8 7 6 5 8 7 6 5 8 7 330 330 330 330 330 330 330 330 330 330 330 330 E RN53 RN56 RN56 3.3 V RN63 RN63 RN63 RN63 RN64 RN64 RN64 RN64 1 2 3 4 1 2 3 4 RES_ARRAY_4 28G9> 3E10> 7E9< 3E10> XCLK\I TDO1\I TDO2 JTAG<2..0>\I TEMUX PM8315 2 OF 2 8 7 6 5 8 7 6 5 10K 10K 10K 10K 10K 10K 10K 10K E 16F4<13F4<10F3<9D9> 7D9> 16E4<13E4<10E4<9D9> 7D9> SBI_DV5\I SBI_DPL\I RN37 RN57 4 1 5 8 22 22 D 16E4<13E4<10E4<9D9> 7D9> SBI_DDP\I RN57 2 7 22 A9 D8 K2 K1 J20 J22 R22 U19 D9 E1 V1 W4 J19 K20 Y22 V20 G1 F4 W1 Y1 K21 K22 W21 Y21 AA22 W20 V3 AB5 C22 D22 IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1 TEMUXSELB D C 29D9< C RECVCLK1\I VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1> E2 L4 V2 AA4 Y9 W11 Y14 Y17 AA19 V21 M20 J21 E21 B18 D15 C11 B8 C6 AA2 J14 J13 J12 J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11 VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> B DRAWING: TEMUX_1.2 TMX1 Thu Nov 22 15:05:29 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN TEMUX-1.2 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:5 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS 3.3 V 0.01UF C110 0.01UF C106 0.01UF C104 0.01UF 2.5 V ZONE C100 0.01UF REV DESCRIPTION DATE APPR C109 0.01UF C108 0.01UF C107 0.01UF C105 0.01UF 0.01UF C102 0.01UF C101 0.01UF C103 C99 H H G RN56 RN56 RN69 3 4 1 6 5 8 330 330 330 G 3.3 V AA12 AA15 2.5 V L21 C12 AA8 R21 H21 A15 N2 J2 R2 PBGA U4 28F3> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> VDD2V5<8> VDD2V5<7> VDD2V5<6> VDD2V5<5> VDD2V5<4> VDD2V5<3> VDD2V5<2> VDD2V5<1> C9 LREFCLK\I TELECOM_AD<7..0>\I 7 6 5 4 3 2 1 0 CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1> P1 N1 P4 M3 N4 M2 C5 A4 L2 L1 B5 A5 E22 C20 B6 D4 M1 P2 C7 D6 M22 N19 B4 A3 R4 T2 A2 A7 N22 N21 N20 P19 AA3 AB4 F2 E4 K4 L3 D20 B22 U22 T20 F1 D3 R1 U4 C21 D21 V19 U21 G3 G2 T1 AB1 T22 T21 V22 AB22 AA21 Y19 Y4 AB3 7 6 F 3D10< 8F9> 4F9> RN65 RN65 RN65 RN65 RN66 RN66 RN66 RN66 RN67 RN67 1 2 3 4 1 2 3 4 1 2 8 7 6 5 8 7 6 5 8 7 22 22 22 22 22 22 22 22 22 22 28F3> 3D10<8F9> 4F9> 3D10<8F9> 4F9> LAC1\I TELECOM_ADP\I TELECOM_APL\I 3.3 V 4.7K R31 W12 AB10 AA10 Y10 W9 AB9 W8 W7 AB8 W13 AA11 W10 Y11 AB11 AB7 W6 AA6 AA7 A16 D16 B16 C15 D17 D13 A13 B13 C13 D14 A14 B14 C14 B21 C19 A21 B20 B19 C18 A20 A19 A18 B17 D19 D18 C16 A17 A22 LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB CSB RDB WRB ALE D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB CICLK<1>\I CTCLK<0>\I CECLK<1>\I SBI_AD<7..0>\I RN78 RN81 5 4 4 1 2 3 4 1 5 8 7 6 5 8 29C4> 29C4> 29C4> 10G9> 13G9> 16G9> F 330 330 330 330 330 330 E RN81 RN81 3 2 RN81 RN82 1 0 E 9 4 7 6 1 TE2_INTB TE2_CSB TE_RDB TE_WRB TE2_ALE 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RN69 RN69 RN69 RN70 RN70 RN70 RN70 RN71 RN71 RN71 RN71 RN72 RN72 RN72 RN72 RN73 RN73 RN73 RN73 RN74 RN74 RN74 RN74 RN75 RN75 RN75 RN75 RN76 RN76 RN76 RN76 RN77 RN77 RN77 RN77 RN78 RN78 RN78 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 330 330 SBI_APL\I SBI_AV5\I 330 330 SBI_ADP\I TEMUX1_SBIACT 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 10E9> 13E9> 16E9> 10F9> 13F9> 16F9> 10F9> 13F9> 16F9> 5F3> 28D3<> 8E9<> 4E9<> TEMUX_UP_CONTROL<10..0>\I TEMUX PM8315 1 OF 2 17F5<> 14F5<> 11F5<> 8D9<> 4D9<> 3B10<> 22C4<> 21D10<> 28C3<> 25G3<> L_AD<31..0>\I D D UNUSED INPUTS 28F3> CHIP_ADDRESS<19..0>\I RSTB\I 29B5<> 28B3<> 26C5> 22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 4D9<> 3C10<> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12 P11 P10 P9 N3 Y12 L20 B12 VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> C VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1> C J3 R3 Y8 Y15 R20 H20 B15 B9 B B DRAWING: TEMUX_2.1 TMX2 Thu Nov 22 15:05:32 2001 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN TEMUX-2.1 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:6 1 OF 29 A 10 3.3 V 0.01UF C123 0.01UF C122 0.01UF C121 0.01UF C120 0.01UF C119 0.01UF C118 0.01UF C117 0.01UF C116 0.01UF C115 0.01UF 9 8 7 6 5 4 3 2 1 REVISIONS C114 0.01UF C113 0.01UF C112 0.01UF ZONE C111 REV DESCRIPTION DATE APPR H H G 3.3 V AA14 G AA9 Y18 U20 M21 F20 C17 PBGA U4 28E3> B11 F3 M4 U3 Y5 VDD3V3<9> VDD3V3<8> VDD3V3<7> VDD3V3<6> VDD3V3<5> VDD3V3<4> VDD3V3<3> VDD3V3<2> VDD3V3<13> VDD3V3<12> VDD3V3<11> CLK52M\I P3 VDD3V3<10> VDD3V3<1> D5 3E10> TELECOM_DD<7..0>\I 7 6 5 4 3 2 1 0 W17 AB15 W16 W15 AB14 W14 Y13 AA13 Y16 AB16 AA16 AB17 AB12 AB13 AA17 AB18 W18 AA18 AB19 W19 W5 Y7 AB6 E20 C3 C2 C4 B3 B1 CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TCK TMS TDI TDO TRSTB CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1> T4 B7 A6 D7 A8 C8 C10 B10 H4 J1 A10 D10 L19 M19 A11 D11 V4 U2 D12 A12 P22 P21 H2 G4 W2 Y2 G21 G22 P20 R19 T19 AA20 Y6 AA5 D2 E3 J4 K3 F21 E19 G19 H19 C1 D1 U1 T3 G20 F22 K19 L22 H1 H3 AA1 W3 F19 H22 Y20 W22 AB21 AB20 AB2 Y3 F RN88 RN88 RN88 RN90 RN90 RN90 RN90 RN93 RN93 RN93 2 3 4 1 2 3 4 1 2 3 RES_ARRAY_4 7 6 5 8 7 6 5 8 7 6 22 22 22 22 22 22 22 22 22 22 7 6 5 4 3 2 1 0 SREFCLK\I C1FP\I ADJUST\I TEMUX2_SBIACT TEMUX3_SBIACT SBI_DD<7..0>\I 28F3> 28F3> 5F3> 9F3> 10F3<13F4<16F4< 5F3< 9F3< 9F3> 5F3> 9F3> 10F3<13F4<16F4< F 3D10> 3D10> 3E10> TELECOM_DC1J1V1\I TELECOM_DDP\I TELECOM_DPL\I RN82 RN82 RN82 RN83 RN83 RN83 RN83 RN84 RN84 2 3 4 1 2 3 4 1 2 3 4 1 7 6 5 8 7 6 5 8 7 6 5 8 330 330 330 330 330 330 330 330 330 330 330 330 0 1 2 E RN84 RN84 RN87 28G9> 5E9> 9E9< 3E10> E XCLK\I TDO2 TDO3 JTAG<2..0>\I TEMUX PM8315 2 OF 2 16F4<13F4<10F3<9D9> 5D9> 16E4<13E4<10E4<9D9> 5D9> SBI_DV5\I SBI_DPL\I RN67 RN67 3 4 6 5 22 22 D 16E4<13E4<10E4<9D9> 5D9> SBI_DDP\I 1 RN88 8 22 A9 D8 K2 K1 J20 J22 R22 U19 D9 E1 V1 W4 J19 K20 Y22 V20 G1 F4 W1 Y1 K21 K22 W21 Y21 AA22 W20 V3 AB5 C22 D22 IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1 TEMUXSELB D AA2 J14 J13 J12 J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11 E2 L4 V2 AA4 Y9 W11 Y14 Y17 AA19 V21 M20 J21 E21 B18 D15 C11 B8 C6 VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1> C C VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> B DRAWING: TEMUX_2.2 TMX2 Thu Nov 22 15:05:34 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN TEMUX-2.2 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:7 1 OF 29 A 10 3.3 V 0.01UF C135 0.01UF C134 0.01UF C133 0.01UF C132 0.01UF C131 0.01UF 9 8 2.5 V 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR C127 0.01UF C126 0.01UF C125 0.01UF C124 C130 0.01UF C129 0.01UF C128 0.01UF H H G RN87 RN87 RN87 2 3 4 7 6 5 330 330 330 G 3.3 V AA12 AA15 L21 C12 AA8 R21 H21 A15 2.5 V N2 J2 R2 PBGA U5 28F3> 3D10< 6F9> 4F9> VDDQ<4> VDDQ<3> VDDQ<2> VDD2V5<8> VDD2V5<7> VDD2V5<6> VDD2V5<5> VDD2V5<4> VDD2V5<3> VDD2V5<2> VDD2V5<1> LREFCLK\I TELECOM_AD<7..0>\I 7 6 5 4 3 2 1 0 VDDQ<1> C9 CSSED CICLK CIFP CTCLK CECLK CEFP ED<28> ED<27> ED<26> ED<25> ED<24> ED<23> ED<22> ED<21> ED<20> ED<19> ED<18> ED<17> ED<16> ED<15> ED<14> ED<13> ED<12> ED<11> ED<10> ED<9> ED<8> ED<7> ED<6> ED<5> ED<4> ED<3> ED<2> ED<1> ECLK<28> ECLK<27> ECLK<26> ECLK<25> ECLK<24> ECLK<23> ECLK<22> ECLK<21> ECLK<20> ECLK<19> ECLK<18> ECLK<17> ECLK<16> ECLK<15> ECLK<14> ECLK<13> ECLK<12> ECLK<11> ECLK<10> ECLK<9> ECLK<8> ECLK<7> ECLK<6> ECLK<5> ECLK<4> ECLK<3> ECLK<2> ECLK<1> P1 N1 P4 M3 N4 M2 C5 A4 L2 L1 B5 A5 E22 C20 B6 D4 M1 P2 C7 D6 M22 N19 B4 A3 R4 T2 A2 A7 N22 N21 N20 P19 AA3 AB4 F2 E4 K4 L3 D20 B22 U22 T20 F1 D3 R1 U4 C21 D21 V19 U21 G3 G2 T1 AB1 T22 T21 V22 AB22 AA21 Y19 Y4 AB3 7 6 F RN93 RN96 RN96 RN96 RN96 RN97 RN97 RN97 RN97 RN98 4 1 2 3 4 1 2 3 4 1 5 8 7 6 5 8 7 6 5 8 22 22 22 22 22 22 22 22 22 22 28F3> 3D10<6E9> 4F9> 3D10<6E9> 4F9> LAC1\I TELECOM_ADP\I TELECOM_APL\I 3.3 V 4.7K R32 W12 AB10 AA10 Y10 W9 AB9 W8 W7 AB8 W13 AA11 W10 Y11 AB11 AB7 W6 AA6 AA7 A16 D16 B16 C15 D17 LREFCLK LADATA<7> LADATA<6> LADATA<5> LADATA<4> LADATA<3> LADATA<2> LADATA<1> LADATA<0> LAC1 LAC1J1V1 LADP LAPL LAOE TPOS_TDAT TNEG_TMFP TICLK TCLK INTB CSB RDB WRB ALE D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> RSTB CICLK<2>\I 29C4> CTCLK<1>\I 29C4> CECLK<2>\I 29C4> SBI_AD<7..0>\I 10G9> 13G9> 16G9> RN122 RN122 5 4 3 4 1 2 3 4 6 5 8 7 6 5 F 330 330 330 330 330 330 RN130 RN130 3 2 RN130 RN130 1 0 8 TE3_INTB TE3_CSB TE_RDB TE_WRB TE3_ALE 7 6 5 4 3 2 1 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E 28D3<> 6E9<> 4E9<> RN113 RN113 RN113 RN113 RN114 RN114 RN114 RN114 RN115 RN115 RN115 RN115 RN116 RN116 RN116 RN116 RN117 RN117 RN117 RN117 RN118 RN118 RN118 RN118 RN119 RN119 RN119 RN119 RN120 RN120 RN120 RN120 RN121 RN121 RN121 RN121 RN122 RN122 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 330 330 SBI_APL\I SBI_AV5\I 330 330 SBI_ADP\I TEMUX1_SBIACT 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 330 10E9> 13E9> 16E9> 10F9> 13F9> 16F9> 10F9> 13F9> 16F9> 5F3> TEMUX_UP_CONTROL<10..0>\I 5 7 6 2 E 25G3<> 22C4<> 21D10<> 17F5<> 14F5<> 11F5<> 6D9<> 4D9<> 3B10<> 28C3<> L_AD<31..0>\I D13 A13 B13 C13 D14 A14 B14 C14 B21 C19 A21 B20 B19 C18 A20 A19 A18 B17 D19 D18 C16 A17 A22 TEMUX PM8315 1 OF 2 D D UNUSED INPUTS 28F3> 29B5<> 28B3<> 26C5> 22B8<> 21E6<> 17E6<> 14E5<> 11E5<> 4D9<> 3C10<> CHIP_ADDRESS<19..0>\I RSTB\I C VSS2V5<8> VSS2V5<7> VSS2V5<6> VSS2V5<5> VSS2V5<4> VSS2V5<3> VSS2V5<2> VSS2V5<1> VSS<20> VSS<19> VSS<18> VSS<17> VSS<16> VSS<15> VSS<14> VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> VSSQ<4> VSSQ<3> VSSQ<2> VSSQ<1> C L10 L9 M14 M13 M12 M11 M10 M9 N14 N13 N12 N11 N10 N9 P14 P13 P12 P11 P10 P9 N3 Y12 L20 B12 J3 R3 Y8 Y15 R20 H20 B15 B9 B DRAWING: TEMUX_1.3 TMX3 Thu Nov 22 15:05:37 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN TEMUX-3.1 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:8 1 OF 29 A 10 3.3 V 0.01UF C148 0.01UF C147 0.01UF C146 0.01UF C145 0.01UF C144 0.01UF C143 0.01UF C142 0.01UF C141 0.01UF C140 0.01UF 9 8 7 6 5 4 3 2 1 REVISIONS C139 0.01UF C138 0.01UF C137 0.01UF ZONE C136 REV DESCRIPTION DATE APPR H H G 3.3 V AA14 G AA9 Y18 U20 M21 F20 C17 PBGA U5 B11 F3 M4 U3 Y5 VDD3V3<9> VDD3V3<8> VDD3V3<7> VDD3V3<6> VDD3V3<5> VDD3V3<4> VDD3V3<3> VDD3V3<2> VDD3V3<13> VDD3V3<12> VDD3V3<11> 28E3> 3E10> CLK52M\I P3 VDD3V3<10> VDD3V3<1> D5 TELECOM_DD<7..0>\I 7 6 5 4 3 2 1 0 W17 AB15 W16 W15 AB14 W14 Y13 AA13 Y16 AB16 AA16 AB17 AB12 AB13 AA17 AB18 W18 AA18 AB19 W19 W5 Y7 AB6 E20 0 1 2 C3 C2 C4 B3 B1 CLK52M LDDATA<7> LDDATA<6> LDDATA<5> LDDATA<4> LDDATA<3> LDDATA<2> LDDATA<1> LDDATA<0> LDC1J1 LDDP LDPL LDV5 LDAIS LDTPL RADEASTCLK RADEASTFP RADEAST RADWESTCLK RADWESTFP RADWEST RCLK RPOS/RDAT RNEG/RLCV XCLK TCK TMS TDI TDO TRSTB CCSID SREFCLK SC1FP SAJUST_REQ SBIACT SBIDET0 ID<28> ID<27> ID<26> ID<25> ID<24> ID<23> ID<22> ID<21> ID<20> ID<19> ID<18> ID<17> ID<16> ID<15> ID<14> ID<13> ID<12> ID<11> ID<10> ID<9> ID<8> ID<7> ID<6> ID<5> ID<4> ID<3> ID<2> ID<1> ICLK<28> ICLK<27> ICLK<26> ICLK<25> ICLK<24> ICLK<23> ICLK<22> ICLK<21> ICLK<20> ICLK<19> ICLK<18> ICLK<17> ICLK<16> ICLK<15> ICLK<14> ICLK<13> ICLK<12> ICLK<11> ICLK<10> ICLK<9> ICLK<8> ICLK<7> ICLK<6> ICLK<5> ICLK<4> ICLK<3> ICLK<2> ICLK<1> T4 B7 A6 D7 A8 C8 SREFCLK\I C1FP\I RN134 RN134 1 2 3 4 1 2 3 4 1 2 RES_ARRAY_4 28F3> 28F3> 5F3> 7F3<> 10F3< 13F4< 16F4< 4E3< 7F3< 7F3> 5F3>7F3> 10F3<13F4<16F4< F 8 7 6 5 8 7 6 5 8 7 22 22 22 22 22 22 22 22 22 22 7 6 5 4 3 2 1 0 3D10> 3D10> 3E10> TELECOM_DC1J1V1\I TELECOM_DDP\I TELECOM_DPL\I RN131 RN131 RN131 RN131 RN132 RN132 RN132 RN132 RN133 1 2 3 4 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 8 7 6 5 330 330 330 330 330 330 330 330 330 330 330 330 E RN133 RN133 RN133 28G9> 7E9> 11E5< 3E10> XCLK\I TDO3 TDO4\I JTAG<2..0>\I TEMUX PM8315 2 OF 2 C10 RN134 B10 RN134 H4 J1 A10 RN135 D10 RN135 L19 M19 A11 RN135 D11 RN135 V4 U2 D12 RN136 A12 RN136 P22 P21 H2 G4 W2 Y2 G21 G22 P20 R19 T19 AA20 Y6 AA5 D2 E3 J4 K3 F21 E19 G19 H19 C1 D1 U1 T3 G20 F22 K19 L22 H1 H3 AA1 W3 F19 H22 Y20 W22 AB21 AB20 AB2 Y3 ADJUST\I TEMUX3_SBIACT TEMUX2_SBIACT SBI_DD<7..0>\I F E 16F4<13F4<10F3<7D9> 5D9> 16E4<13E4<10E4<7D9> 5D9> SBI_DV5\I SBI_DPL\I RN98 RN98 2 3 7 6 D 16E4<13E4<10E4<7D9> 5D9> SBI_DDP\I RN98 4 A9 D8 K2 K1 J20 J22 R22 U19 5 22 D9 E1 V1 W4 J19 K20 Y22 V20 G1 F4 W1 Y1 K21 K22 W21 Y21 AA22 W20 V3 AB5 C22 D22 22 22 IFP<28> IFP<27> IFP<26> IFP<25> IFP<24> IFP<23> IFP<22> IFP<21> IFP<20> IFP<19> IFP<18> IFP<17> IFP<16> IFP<15> IFP<14> IFP<13> IFP<12> IFP<11> IFP<10> IFP<9> IFP<8> IFP<7> IFP<6> IFP<5> IFP<4> IFP<3> IFP<2> IFP<1> RECVCLK2 RECVCLK1 TEMUXSELB D AA2 J14 J13 J12 J11 J10 J9 K14 K13 K12 K11 K10 K9 L14 L13 L12 L11 E2 L4 V2 AA4 Y9 W11 Y14 Y17 AA19 V21 M20 J21 E21 B18 D15 C11 B8 C6 VSS3V3<18> VSS3V3<17> VSS3V3<16> VSS3V3<15> VSS3V3<14> VSS3V3<13> VSS3V3<12> VSS3V3<11> VSS3V3<10> VSS3V3<9> VSS3V3<8> VSS3V3<7> VSS3V3<6> VSS3V3<5> VSS3V3<4> VSS3V3<3> VSS3V3<2> VSS3V3<1> C C VSS<36> VSS<35> VSS<34> VSS<33> VSS<32> VSS<31> VSS<30> VSS<29> VSS<28> VSS<27> VSS<26> VSS<25> VSS<24> VSS<23> VSS<22> VSS<21> B DRAWING: TEMUX_3.2 TMX3 Thu Nov 22 15:05:40 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN TEMUX-3.2 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:9 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H 12D2<> H AAL1_RAM2_D<15..0> U12 AAL1GATOR-32 PM73122 1 OF 5 TL_SYNC15 TL_SYNC14 TL_SYNC13 TL_SYNC12 TL_SYNC11 TL_SYNC10 TL_SYNC9 TL_SYNC8 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA15 TL_DATA14 TL_DATA13 TL_DATA12 TL_DATA11 TL_DATA10 TL_DATA9 TL_DATA8 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG15 TL_SIG14 TL_SIG13 TL_SIG12 TL_SIG11 TL_SIG10 TL_SIG9 TL_SIG8 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK15 TL_CLK14 TL_CLK13 TL_CLK12 TL_CLK11 TL_CLK10 TL_CLK9 TL_CLK8 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE1 LINE_MODE0 LINE INTERFACE RN139 12D7< 1 AAL1_RAM2_A<17..0> 14 11 7 6 2 12B7< 12C7< 6F2< 4F3< 16G9> 13G9> 8F3< AAL1_RAM2_OEB AAL1_RAM2_CSB RN141 RN141 SBI_AD<7..0>\I 19 18 17 16 17 15 12 8 4 3 0 7 4 2 3 G 12C7< AAL1_RAM2_WE0B RN139 RN139 6 3 1 2 3 6E2< 8E2< 6E2< 4E3< 4E3< 16F9> 13F9> 8E2< 13F9> 16F9> 28E9< SBI_ADP\I SBI_AV5\I AACTIVE<1>\I 16 13 10 9 5 1 F 12C7< 12B7< AAL1_RAM2_WE1B AAL1_RAM2_R/WB RN139 RN140 RN140 5 2 0 4 1 2 8E2< 6E2< 4E3< 13E9> 16E9> SBI_APL\I RN140 31 30 29 28 27 26 25 24 23 22 21 20 3 E RN140 29C4> 28E3> 4 1 RL_CLK<5..0>\I FASTCLK\I 1 RN141 0 N24 AE15 AF8 Y4 AB1 M2 C7 B11 7 330 C4 6 330 E2 G2 K3 R1 U2 W2 AB4 AD16 AD15 AE9 AA3 Y3 M1 B6 C11 D3 7 330 F3 6 330 H3 J1 R2 T4 Y1 AC3 AE16 AF15 AC10 AB2 AA2 M3 D8 D12 A3 5 330 F4 8 330 H4 7 330 H1 P3 U1 U4 6 330 AC2 N23 P25 R24 R23 K23 H25 B15 A16 D5 D1 F1 J2 L1 5 330 T3 V3 8 330 AD1 B7 8 330 RL_SYNC15 RL_SYNC14 RL_SYNC13 RL_SYNC12 RL_SYNC11 RL_SYNC10 RL_SYNC9 RL_SYNC8 RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA15 RL_DATA14 RL_DATA13 RL_DATA12 RL_DATA11 RL_DATA10 RL_DATA9 RL_DATA8 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG15 RL_SIG14 RL_SIG13 RL_SIG12 RL_SIG11 RL_SIG10 RL_SIG9 RL_SIG8 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK15 RL_CLK14 RL_CLK13 RL_CLK12 RL_CLK11 RL_CLK10 RL_CLK9 RL_CLK8 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK K24 AC15 AC11 AF7 AA1 N3 A5 B10 A4 E4 G4 G1 L4 R3 V1 W3 J26 AF16 AF9 AD9 P2 M4 C6 A9 B4 E3 G3 K4 K1 T2 W1 AB3 L23 AC14 AD10 AE8 N2 L2 D7 D11 C5 D2 F2 J3 L3 R4 V2 AA4 J25 N25 R25 T26 H26 J24 A15 C15 D6 C1 E1 H2 K2 T1 U3 Y2 C8 B5 AC1 RN143 RN144 15 10 9 7 2 0 4 1 5 8 330 330 RN141 RN142 RN142 RN142 RN142 RN143 RN143 RN143 14 12 8 6 4 1 6 4 2 0 4 1 2 3 4 1 2 3 5 8 7 6 5 8 7 6 330 330 330 330 330 330 330 330 G SBI_DD<7..0>\I 5F3> 7F3> 9F3> SBI_DV5\I ADJUST\I C1FP\I 13 11 1 5 3 0 7 5 3 1 5D9> 7D9> 9D9> 5F3> 7F3<> 9F3> 28F3> F AAL1_RAM2_PAR<1..0> 12D2<> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SBI_DDP\I SBI_DPL\I ADETECT<1>\I TL_CLK<95..0>\I 5D9> 7D9> 9D9> 5D9> 7D9> 9D9> 28E9> 29D4> E SREFCLK\I 3.3 V 28F3> D D U12 19G9> ANYPHY_TDAT<15..0>\I 19E9> 19F9> ANYPHY_TSX\I ANYPHY_TADR<3..0>\I R33 C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 19E9> 19E9> 19E9< 16B9> 13B8> ANYPHY_TPAR\I ANYPHY_TENB\I ANYPHY_TPA\I AB24 AA23 AC26 AB25 Y23 AB26 AA25 Y24 V25 U24 V26 T23 T24 U26 T25 R26 AA24 W23 W24 W25 V24 Y25 U25 U23 RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV AAL1GATOR-32 PM73122 5 OF 5 820 R34 TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 RATM_CLK RATM_SOC TATM_PAR TATM_ENB TATM_CLAV TATM_CLK TATM_SOC D24 E23 C26 D25 F23 D26 E25 F24 K25 L24 K26 L25 P24 M24 M25 M26 E24 G24 F25 H23 G25 Y26 W26 E26 H24 M23 F26 G26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 RDAT<15..0>\I 13C3> 16C3> 27D7> 22G3< 4.7K 4.7K R35 C RADR<4..0>\I 22F3> TPHY_CLK\I RSOC\I RPRTY\I RDENB\I RCA\I RPHY_CLK\I 24D4> 27C7> 13B3> 16B3> 27C7> 22F3< 13B3> 16B3> 27B7> 22F3< 24D4> R36 820 B UTOPIA INTERFACE B DRAWING: AAL1GATOR_32_1.1 AAL1 Thu Nov 22 15:05:43 2001 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN AAL1GATOR-32_1 LINE-UTOPIA INTER. ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:10 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G U6 28F3> G CHIP_ADDRESS<19..0>\I F 29D9< 14E9> 17E9> 29D9< 14E9> 17E9> 29C9< 29C9< 29B9> E 29C4> 29C4> AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 CGC_DOUT<11..0>\I AC8 AF10 AE7 AD8 AD5 CGC_LINES<14..0>\I AC6 AF4 3.3 V AE5 AD6 AF3 SRTS_STRB<0>\I ADAP_STRB<0>\I AE4 AD7 NCLK<0>\I RN145 AE6 1 8 4.7K AC7 CGC_SER_D<0>\I AF5 CGC_VALID<0>\I 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 4 3 2 1 0 AAL1GATOR-32 PM73122 2 OF 5 A19 A18 A17 A16 A15 D15 A14 D14 A13 D13 A12 D12 A11 D11 A10 D10 D9 A9 D8 A8 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0 CGC_DOUT3 ALE CGC_DOUT2 WRB CGC_DOUT1 RDB CGC_DOUT0 CSB CGC_LINE4 ACKB CGC_LINE3 INTB CGC_LINE2 TRSTB CGC_LINE1 RSTB CGC_LINE0 SYSCLK SCAN_MODEB SRTS_STBH TCLK ADAP_STBH NCLK TMS TL_CLK_OE TDI CGC_SER_D TDO CGC_VALID MICRO/JTAG 3.3 V 25G3<> 28C3<> 14F5<> 17F5<> 3B10<> 4D9<> 6D9<> 8D9<> 21D10<> 22C4<> V23 V4 P23 N4 J4 J23 D23 D18 D14 D9 D4 C24 C3 B25 B2 AE25 AE2 AD24 AD3 AC23 AC18 AC13 AC9 AC4 A21 A10 P4 W4 AF6 AF17 AA26 L26 G23 U6 AAL1GATOR-32 PM73122 VDD23 3 OF 5 VSS27 VSS26 VDD22 VSS25 VDD21 VSS24 VDD20 VSS23 VDD19 VSS22 VDD18 VSS21 VDD17 VSS20 VDD16 VSS19 VDD15 VSS18 VDD14 VSS17 VDD13 VSS16 VDD12 VSS15 VDD11 VSS14 VDD10 VSS13 VDD9 VSS12 VDD8 VSS11 VDD7 VSS10 VDD6 VSS9 VDD5 VSS8 VDD4 VSS7 VDD3 VSS6 VDD2 VSS5 VDD1 VSS4 VDD0 VSS3 PCH_9 VSS2 PCH_8 VSS1 PCH_7 VSS0 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 POWER SUPPLY AF26 AF25 AF14 AF13 AF2 AF1 AE26 AE3 AE24 AE1 AD25 AD2 P26 P1 N26 N1 C25 C2 B26 B24 B3 B1 A26 A25 A14 A13 A2 A1 AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AD12 AF11 AC12 AE11 AD11 AE10 AC5 AD4 B23 AC24 D22 A24 C23 A23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L_AD<31..0>\I 3.3 V F RN145 RN145 RN145 10 6 5 7 3 0 2 3 4 7 6 5 4.7K 4.7K 4.7K 28E3<> 17E6<> 14E5<> AAL1_ALE AAL_WRB AAL_RDB AAL1_CSB AAL1_ACKB AAL1_INTB 2 AAL_UP_CONTROL<13..0>\I RSTB\I 0 1 8D9< 22B8<> 26C5> 3C10<> 4D9<> 14E5<> 17E6<> 21E6<> 28B3<> 29B5<> 6C9< 3E10> 9E9> 2.5 V JTAG<2..0>\I TDO4\I TDO5 E 3.3 V 50PPM 3.3V 38.880MHZ HCMOS Y7 8 U43 13 12 ACT125 11 56 R66 AAL_SYSCLK\I 14E5<17E6<29B9< VDD OUT 5 1 56 R65 0.01UF 0.1UF C149 C150 4 GND NC/TS U43 10 9 ACT125 D 8 56 R67 D RAM1_CLK 12E7<15E8< 18E7< U43 4 5 ACT125 6 56 R68 RAM2_CLK 12B7<15B8<18B7< C 3.3 V 2.5 V C 0.01UF C167 0.01UF C166 0.01UF C165 0.01UF C164 0.01UF C163 0.01UF C162 0.01UF C161 0.01UF C160 0.01UF C159 0.01UF C158 0.01UF C157 0.01UF 0.01UF 0.01UF 0.01UF C153 0.01UF C152 0.01UF C156 C155 C154 DECOUPLING CAPS ONE CAP PER TWO POWER PINS C151 B DRAWING: AAL1GATOR_32_1.2 AAL1 Thu Nov 22 15:05:45 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN AAL1GATOR-32_1 POWER AND UP ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:11 1 OF 29 A 10 9 8 7 6 5 3.3 V 0.01UF C173 0.01UF C172 0.01UF 0.01UF C170 0.01UF C169 0.01UF 4 3 2 1 REVISIONS C171 C168 ZONE REV DESCRIPTION DATE APPR H H AAL1_RAM1_D<15..0> 3.3 V 91 66 65 41 16 15 80MHZ U7 AAL1_RAM1_A<17..0> 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> 77 70 61 54 27 20 14 11 4 G G U6 AAL1GATOR-32 PM73122 4 OF 5 17A18 16C17 15B18 14A19 13D17 12C18 11B19 10A20 9 B20 8 A17 7 D19 6 C20 5 A22 4 D20 3 C21 2 B22 1 D21 0 C22 F RAM1_A17 RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0 11D5> RAM1_CLK RAM INTERFACE E 3.3 V RN146 1 8 VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB A7 B8 C9 D10 B9 C10 A6 A11 B12 A12 D13 C13 B13 B14 C14 D15 A8 B16 D16 C19 B21 C16 B17 C12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.3 V A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 1 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 NOTE: ZBT RAMS ARE USED IN THIS DESIGN. NON-ZBT RAMS CAN BE USED IN LOWER PERFORMANCE APPLICATIONS. REFER TO PMC DOCUMENT PMC-1990887. F CY71352 (256K X 18) AAL1_RAM1_WE1B AAL1_RAM1_WE0B RN146 AAL1_RAM1_OEB AAL1_RAM1_CSB AAL1_RAM1_R/WB 2 7 4.7K 1 0 RN146 3 6 4.7K BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE E 4.7K AAL1_RAM1_PAR<1..0> 3.3 V D 91 66 65 41 16 15 90 76 71 67 64 60 55 40 26 21 17 10 5 D 80MHZ U8 10H9> 77 70 61 54 27 20 14 11 4 VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> AAL1_RAM2_A<17..0> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> C 3.3 V 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 1 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 AAL1_RAM2_PAR<1..0> AAL1_RAM2_D<15..0> 10F3<> 10H9<> C CY71352 (256K X 18) 10F9> 10F9> 10G9> 10G9> 10F9> 11D5> AAL1_RAM2_WE1B AAL1_RAM2_WE0B AAL1_RAM2_CSB RN147 AAL1_RAM2_OEB AAL1_RAM2_R/WB RAM2_CLK RN147 4 5 3 6 4.7K 4.7K B VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE B DRAWING: AAL1GATOR_32_1.3 AAL1 Thu Nov 22 15:05:48 2001 3.3 V 90 76 71 67 64 60 55 40 26 21 17 10 5 PMC-Sierra, Inc. 0.01UF C179 0.01UF C178 0.01UF 0.01UF C176 0.01UF C175 0.01UF C177 C174 A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN AAL1GATOR-32_1 SRAM INTERFACE ENGINEER: BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:12 1 OF 29 A 10 9 8 7 6 5 4 3 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H 15D2<> H AAL2_RAM2_D<15..0> U9 AAL1GATOR-32 PM73122 1 OF 5 TL_SYNC15 TL_SYNC14 TL_SYNC13 TL_SYNC12 TL_SYNC11 TL_SYNC10 TL_SYNC9 TL_SYNC8 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA15 TL_DATA14 TL_DATA13 TL_DATA12 TL_DATA11 TL_DATA10 TL_DATA9 TL_DATA8 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG15 TL_SIG14 TL_SIG13 TL_SIG12 TL_SIG11 TL_SIG10 TL_SIG9 TL_SIG8 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK15 TL_CLK14 TL_CLK13 TL_CLK12 TL_CLK11 TL_CLK10 TL_CLK9 TL_CLK8 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE1 LINE_MODE0 LINE INTERFACE RN144 15D8< 2 AAL2_RAM2_A<17..0> 14 11 7 6 2 15B8< 15B8< 6F2< 4F3< 16G9> 10G9> 8F3< AAL2_RAM2_OEB AAL2_RAM2_CSB RN150 RN150 SBI_AD<7..0>\I 51 50 49 48 17 15 12 8 4 3 0 7 4 3 4 G 15C8< AAL2_RAM2_WE0B RN144 RN144 6 3 1 3 4 8E2< 6E2< 4E3< 6E2< 4E3< 16F9> 10F9> 8E2< 10F9> 16F9> 28E9< SBI_ADP\I SBI_AV5\I AACTIVE<2>\I 16 13 10 9 5 1 F 15C8< 15B8< AAL2_RAM2_WE1B AAL2_RAM2_R/WB RN149 RN149 RN149 5 2 0 1 2 3 8E2< 6E2< 4E3< 10E9> 16E9> SBI_APL\I RN149 63 62 61 60 59 58 57 56 55 54 53 52 4 E RN150 29C4> 28E3> 1 2 RL_CLK<5..0>\I FASTCLK\I 3 RN150 2 N24 AE15 AF8 Y4 AB1 M2 C7 B11 6 330 C4 5 330 E2 G2 K3 R1 U2 W2 AB4 AD16 AD15 AE9 AA3 Y3 M1 B6 C11 6 330 D3 5 330 F3 H3 J1 R2 T4 Y1 AC3 AE16 AF15 AC10 AB2 AA2 M3 D8 D12 A3 8 330 F4 7 330 H4 6 330 H1 P3 U1 U4 5 330 AC2 N23 P25 R24 R23 K23 H25 B15 A16 D5 D1 F1 J2 8 330 L1 T3 7 330 V3 AD1 B7 7 330 RL_SYNC15 RL_SYNC14 RL_SYNC13 RL_SYNC12 RL_SYNC11 RL_SYNC10 RL_SYNC9 RL_SYNC8 RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA15 RL_DATA14 RL_DATA13 RL_DATA12 RL_DATA11 RL_DATA10 RL_DATA9 RL_DATA8 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG15 RL_SIG14 RL_SIG13 RL_SIG12 RL_SIG11 RL_SIG10 RL_SIG9 RL_SIG8 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK15 RL_CLK14 RL_CLK13 RL_CLK12 RL_CLK11 RL_CLK10 RL_CLK9 RL_CLK8 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK K24 AC15 AC11 AF7 AA1 N3 A5 B10 A4 E4 G4 G1 L4 R3 V1 W3 J26 AF16 AF9 AD9 P2 M4 C6 A9 B4 E3 G3 K4 K1 T2 W1 AB3 L23 AC14 AD10 AE8 N2 L2 D7 D11 C5 D2 F2 J3 L3 R4 V2 AA4 J25 N25 R25 T26 H26 J24 A15 C15 D6 C1 E1 H2 K2 T1 U3 Y2 C8 B5 AC1 RN153 RN153 15 10 9 7 2 0 1 2 8 7 330 330 RN151 RN151 RN151 RN151 RN152 RN152 RN152 RN152 14 12 8 6 4 1 6 4 2 0 1 2 3 4 1 2 3 4 8 7 6 5 8 7 6 5 330 330 330 330 330 330 330 330 G SBI_DD<7..0>\I 5F3> 7F3> 9F3> SBI_DV5\I ADJUST\I C1FP\I 13 11 1 5 3 0 7 5 3 1 5D9> 7D9> 9D9> 5F3> 7F3<> 9F3> 28F3> F AAL2_RAM2_PAR<1..0> 15D2<> 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 SBI_DDP\I SBI_DPL\I ADETECT<2>\I TL_CLK<95..0>\I 5D9> 7D9> 9D9> 5D9> 7D9> 9D9> 28E9> 29D4> E SREFCLK\I 3.3 V 28F3> D D U9 19G9> ANYPHY_TDAT<15..0>\I C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 19E9> 19F9> ANYPHY_TSX\I ANYPHY_TADR<3..0>\I 19E9> 19E9> 19E9< 16B9> 10B8> ANYPHY_TPAR\I ANYPHY_TENB\I ANYPHY_TPA\I AB24 AA23 AC26 AB25 Y23 AB26 AA25 Y24 V25 U24 V26 T23 T24 U26 T25 R26 AA24 W23 W24 W25 V24 Y25 U25 U23 RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV AAL1GATOR-32 PM73122 5 OF 5 TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 RATM_CLK RATM_SOC TATM_PAR TATM_ENB TATM_CLAV TATM_CLK TATM_SOC D24 E23 C26 D25 F23 D26 E25 F24 K25 L24 K26 L25 P24 M24 M25 M26 E24 G24 F25 H23 G25 Y26 W26 E26 H24 M23 F26 G26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 RDAT<15..0>\I 10D3> 16C3> 27D7> 22G3< C RADR<4..0>\I 22F3> TPHY_CLK\I RSOC\I RPRTY\I RDENB\I RCA\I RPHY_CLK\I 24D4> 27C7> 10B3> 16B3> 27C7> 22F3< 10B3> 16B3> 27B7> 22F3< 24D4> B UTOPIA INTERFACE DRAWING: AAL1GATOR_32_2.1 AAL2 Thu Nov 22 15:05:50 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN AAL1GATOR-32_2 LINE-UTOPIA INTER. ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:13 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G U9 28F3> 3.3 V AAL1GATOR-32 PM73122 2 OF 5 AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AD12 AF11 AC12 AE11 AD11 AE10 AC5 AD4 B23 AC24 D22 A24 C23 A23 V23 V4 P23 N4 J4 J23 D23 D18 D14 D9 D4 C24 C3 B25 B2 AE25 AE2 AD24 AD3 AC23 AC18 AC13 AC9 AC4 A21 A10 P4 W4 AF6 AF17 AA26 L26 G23 U9 AAL1GATOR-32 PM73122 VDD23 3 OF 5 VSS27 VSS26 VDD22 VSS25 VDD21 VSS24 VDD20 VSS23 VDD19 VSS22 VDD18 VSS21 VDD17 VSS20 VDD16 VSS19 VDD15 VSS18 VDD14 VSS17 VDD13 VSS16 VDD12 VSS15 VDD11 VSS14 VDD10 VSS13 VDD9 VSS12 VDD8 VSS11 VDD7 VSS10 VDD6 VSS9 VDD5 VSS8 VDD4 VSS7 VDD3 VSS6 VDD2 VSS5 VDD1 VSS4 VDD0 VSS3 PCH_9 VSS2 PCH_8 VSS1 PCH_7 VSS0 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 POWER SUPPLY AF26 AF25 AF14 AF13 AF2 AF1 AE26 AE3 AE24 AE1 AD25 AD2 P26 P1 N26 N1 C25 C2 B26 B24 B3 B1 A26 A25 A14 A13 A2 A1 F CHIP_ADDRESS<19..0>\I E 17E9> 11F9> 29D9< 17E9> 11E9> 29D9< 29C9< 29C9< 29B9> 29C4> 29C4> AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 CGC_DOUT<11..0>\I AC8 AF10 AE7 AD8 AD5 CGC_LINES<14..0>\I AC6 AF4 3.3 V AE5 AD6 SRTS_STRB<1>\I AF3 AE4 ADAP_STRB<1>\I AD7 NCLK<1>\I RN148 AE6 4 5 CGC_SER_D<1>\I 4.7K AC7 AF5 CGC_VALID<1>\I 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 7 6 5 4 9 8 7 6 5 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CGC_DOUT3 CGC_DOUT2 CGC_DOUT1 CGC_DOUT0 CGC_LINE4 CGC_LINE3 CGC_LINE2 CGC_LINE1 CGC_LINE0 SRTS_STBH ADAP_STBH NCLK TL_CLK_OE CGC_SER_D CGC_VALID F D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALE WRB RDB CSB ACKB INTB TRSTB RSTB SYSCLK SCAN_MODEB TCLK TMS TDI TDO MICRO/JTAG 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L_AD<31..0>\I 22C4<> 25G3<> 21D10<> 3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 17F5<> 28C3<> 3.3 V RN154 RN154 RN154 11 6 5 8 4 1 1 2 3 8 7 6 4.7K 4.7K 4.7K 28E3<> 11F5<> 17E6<> AAL2_ALE AAL_WRB AAL_RDB AAL2_CSB AAL2_ACKB AAL2_INTB 2 AAL_UP_CONTROL<13..0>\I E 2.5 V RSTB\I AAL_SYSCLK\I 0 1 3C10<> 4D9<> 11E5<> 17E6<> 21E6<> 22B8<> 26C5> 8D9< 11D5> 28B3<> 29B5<> 6C9< 3E10> JTAG<2..0>\I TDO6 TDO7 D D C C 3.3 V 2.5 V 0.01UF 0.01UF C195 0.01UF C194 0.01UF C193 0.01UF C192 0.01UF C191 0.01UF C190 0.01UF C189 0.01UF C188 0.01UF C187 0.01UF C186 0.01UF 0.01UF 0.01UF 0.01UF C182 0.01UF C181 0.01UF C196 C185 C184 C183 DECOUPLING CAPS ONE CAP PER TWO POWER PINS C180 B DRAWING: AAL1GATOR_32_2.2 AAL2 Thu Nov 22 15:05:52 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN AAL1GATOR-32_2 POWER AND UP ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:14 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS 3.3 V ZONE 0.01UF C198 0.01UF C200 0.01UF 0.01UF C204 0.01UF C206 0.01UF C202 C207 REV DESCRIPTION DATE APPR H H AAL2_RAM1_D<15..0> G 80MHZ U18 AAL2_RAM1_A<17..0> 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 3.3 V 91 66 65 41 16 15 77 70 61 54 27 20 14 11 4 G VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> U9 AAL1GATOR-32 PM73122 4 OF 5 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A18 C17 B18 A19 D17 C18 B19 A20 B20 A17 D19 C20 A22 D20 C21 B22 D21 C22 F RAM1_A17 RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0 E RAM INTERFACE 11D5> RAM1_CLK VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB A7 B8 C9 D10 B9 C10 A6 A11 B12 A12 D13 C13 B13 B14 C14 D15 A8 B16 D16 C19 B21 C16 B17 C12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.3 V A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 1 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 F CY71352 (256K X 18) AAL2_RAM1_WE1B AAL2_RAM1_WE0B RN155 AAL2_RAM1_OEB AAL2_RAM1_CSB AAL2_RAM1_R/WB 1 8 4.7K 1 0 RN155 2 7 4.7K BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE E 3.3 V RN154 4 5 4.7K AAL1_RAM1_PAR<1..0> D 3.3 V 91 66 65 41 16 15 90 76 71 67 64 60 55 40 26 21 17 10 5 D 77 70 61 54 27 20 14 11 4 80MHZ U19 13H9> VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> AAL2_RAM2_A<17..0> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> C 3.3 V 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 1 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 AAL2_RAM2_PAR<1..0> AAL2_RAM2_D<15..0> 13F4<> 13H9<> C CY71352 (256K X 18) 13F9> 13F9> 13G9> 13G9> 13F9> 11D5> AAL2_RAM2_WE1B AAL2_RAM2_WE0B AAL2_RAM2_CSB RN156 AAL2_RAM2_OEB AAL2_RAM2_R/WB RAM2_CLK RN156 3 6 2 7 4.7K VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> 4.7K BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE B B DRAWING: AAL1GATOR_32_2.3 AAL2 Thu Nov 22 15:05:55 2001 90 76 71 67 64 60 55 40 26 21 17 10 5 3.3 V PMC-Sierra, Inc. C199 0.01UF 0.01UF C203 0.01UF C205 0.01UF C201 C208 0.01UF C197 0.01UF A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN AAL1GATOR-32_2 SRAM INTERFACE ENGINEER: BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:15 1 OF 29 A 10 9 8 7 6 5 4 3 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H 18D2<> AAL3_RAM2_D<15..0> U6 AAL1GATOR-32 PM73122 1 OF 5 TL_SYNC15 TL_SYNC14 TL_SYNC13 TL_SYNC12 TL_SYNC11 TL_SYNC10 TL_SYNC9 TL_SYNC8 TL_SYNC7 TL_SYNC6 TL_SYNC5 TL_SYNC4 TL_SYNC3 TL_SYNC2 TL_SYNC1 TL_SYNC0 TL_DATA15 TL_DATA14 TL_DATA13 TL_DATA12 TL_DATA11 TL_DATA10 TL_DATA9 TL_DATA8 TL_DATA7 TL_DATA6 TL_DATA5 TL_DATA4 TL_DATA3 TL_DATA2 TL_DATA1 TL_DATA0 TL_SIG15 TL_SIG14 TL_SIG13 TL_SIG12 TL_SIG11 TL_SIG10 TL_SIG9 TL_SIG8 TL_SIG7 TL_SIG6 TL_SIG5 TL_SIG4 TL_SIG3 TL_SIG2 TL_SIG1 TL_SIG0 TL_CLK15 TL_CLK14 TL_CLK13 TL_CLK12 TL_CLK11 TL_CLK10 TL_CLK9 TL_CLK8 TL_CLK7 TL_CLK6 TL_CLK5 TL_CLK4 TL_CLK3 TL_CLK2 TL_CLK1 TL_CLK0 CTL_CLK LINE_MODE1 LINE_MODE0 LINE INTERFACE H RN153 18D7< 3 AAL3_RAM2_A<17..0> 14 11 7 6 2 18B7< 18C7< 6F2< 4F3< 13G9> 10G9> 8F3< AAL3_RAM2_OEB AAL3_RAM2_CSB RN159 RN160 SBI_AD<7..0>\I 83 82 81 80 17 15 12 8 4 3 0 7 4 4 1 G 18C7< AAL3_RAM2_WE0B RN153 RN158 6 3 1 4 1 6E2< 8E2< 6E2< 4E3< 4E3< 13F9> 10F9> 8E2< 10F9> 13F9> 28E9< SBI_ADP\I SBI_AV5\I AACTIVE<3>\I 16 13 10 9 5 1 F 18C7< 18B7< AAL3_RAM2_WE1B AAL3_RAM2_R/WB RN158 RN158 RN158 5 2 0 2 3 4 8E2< 6E2< 4E3< 10E9> 13E9> SBI_APL\I RN159 95 94 93 92 91 90 89 88 87 86 85 84 1 E RN159 29C4> 28E3> 2 3 RL_CLK<5..0>\I FASTCLK\I 5 RN159 4 N24 AE15 AF8 Y4 AB1 M2 C7 B11 5 330 C4 8 330 E2 G2 K3 R1 U2 W2 AB4 AD16 AD15 AE9 AA3 Y3 M1 B6 C11 5 330 D3 8 330 F3 H3 J1 R2 T4 Y1 AC3 AE16 AF15 AC10 AB2 AA2 M3 D8 D12 A3 7 330 F4 6 330 5 330 H4 H1 P3 U1 U4 8 330 AC2 N23 P25 R24 R23 K23 H25 B15 A16 D5 D1 F1 J2 L1 7 330 T3 V3 6 330 AD1 B7 6 330 RL_SYNC15 RL_SYNC14 RL_SYNC13 RL_SYNC12 RL_SYNC11 RL_SYNC10 RL_SYNC9 RL_SYNC8 RL_SYNC7 RL_SYNC6 RL_SYNC5 RL_SYNC4 RL_SYNC3 RL_SYNC2 RL_SYNC1 RL_SYNC0 RL_DATA15 RL_DATA14 RL_DATA13 RL_DATA12 RL_DATA11 RL_DATA10 RL_DATA9 RL_DATA8 RL_DATA7 RL_DATA6 RL_DATA5 RL_DATA4 RL_DATA3 RL_DATA2 RL_DATA1 RL_DATA0 RL_SIG15 RL_SIG14 RL_SIG13 RL_SIG12 RL_SIG11 RL_SIG10 RL_SIG9 RL_SIG8 RL_SIG7 RL_SIG6 RL_SIG5 RL_SIG4 RL_SIG3 RL_SIG2 RL_SIG1 RL_SIG0 RL_CLK15 RL_CLK14 RL_CLK13 RL_CLK12 RL_CLK11 RL_CLK10 RL_CLK9 RL_CLK8 RL_CLK7 RL_CLK6 RL_CLK5 RL_CLK4 RL_CLK3 RL_CLK2 RL_CLK1 RL_CLK0 CRL_CLK K24 AC15 AC11 AF7 AA1 N3 A5 B10 A4 E4 G4 G1 L4 R3 V1 W3 J26 AF16 AF9 AD9 P2 M4 C6 A9 B4 E3 G3 K4 K1 T2 W1 AB3 L23 AC14 AD10 AE8 N2 L2 D7 D11 C5 D2 F2 J3 L3 R4 V2 AA4 J25 N25 R25 T26 H26 J24 A15 C15 D6 C1 E1 H2 K2 T1 U3 Y2 C8 B5 AC1 RN162 RN162 15 10 9 7 2 0 3 4 6 5 330 330 RN160 RN160 RN161 RN161 RN161 RN161 RN162 RN162 14 12 8 6 4 1 6 4 2 0 3 4 1 2 3 4 1 2 6 5 8 7 6 5 8 7 330 330 330 330 330 330 330 330 G SBI_DD<7..0>\I 5F3> 7F3> 9F3> SBI_DV5\I ADJUST\I C1FP\I 13 11 1 5 3 0 7 5 3 1 5D9> 7D9> 9D9> 5F3> 7F3<> 9F3> 28F3> F AAL3_RAM2_PAR<1..0> 18D2<> 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 SBI_DDP\I SBI_DPL\I ADETECT<3>\I TL_CLK<95..0>\I 5D9> 7D9> 9D9> 5D9> 7D9> 9D9> 28E9> 29D4> E SREFCLK\I 3.3 V 28F3> D D U6 19G9> ANYPHY_TDAT<15..0>\I C 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 19E9> 19F9> ANYPHY_TSX\I ANYPHY_TADR<3..0>\I 19E9> 19E9> 19E9< 13B8> 10B8> ANYPHY_TPAR\I ANYPHY_TENB\I ANYPHY_TPA\I AB24 AA23 AC26 AB25 Y23 AB26 AA25 Y24 V25 U24 V26 T23 T24 U26 T25 R26 AA24 W23 W24 W25 V24 Y25 U25 U23 RATM_D15 RATM_D14 RATM_D13 RATM_D12 RATM_D11 RATM_D10 RATM_D9 RATM_D8 RATM_D7 RATM_D6 RATM_D5 RATM_D4 RATM_D3 RATM_D2 RATM_D1 RATM_D0 TPHY_ADD4 TPHY_ADD3 TPHY_ADD2 TPHY_ADD1 TPHY_ADD0 RATM_PAR RATM_ENB RATM_CLAV AAL1GATOR-32 PM73122 5 OF 5 TATM_D15 TATM_D14 TATM_D13 TATM_D12 TATM_D11 TATM_D10 TATM_D9 TATM_D8 TATM_D7 TATM_D6 TATM_D5 TATM_D4 TATM_D3 TATM_D2 TATM_D1 TATM_D0 RPHY_ADD_RSX RPHY_ADD3 RPHY_ADD2 RPHY_ADD1 RPHY_ADD0 RATM_CLK RATM_SOC TATM_PAR TATM_ENB TATM_CLAV TATM_CLK TATM_SOC D24 E23 C26 D25 F23 D26 E25 F24 K25 L24 K26 L25 P24 M24 M25 M26 E24 G24 F25 H23 G25 Y26 W26 E26 H24 M23 F26 G26 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 RDAT<15..0>\I 10D3> 13C3> 27D7> 22G3< C RADR<4..0>\I 22F3> TPHY_CLK\I RSOC\I RPRTY\I RDENB\I RCA\I RPHY_CLK\I 24D4> 27C7> 10B3> 13B3> 27C7> 22F3< 10B3> 13B3> 27B7> 22F3< 24D4> B UTOPIA INTERFACE DRAWING: AAL1GATOR_32_3.1 AAL3 Thu Nov 22 15:05:57 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN AAL1GATOR-32_3 LINE-UTOPIA INTER. ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:16 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G U12 AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 CHIP_ADDRESS<19..0>\I CGC_DOUT<11..0>\I AC8 AF10 AE7 AD8 AD5 CGC_LINES<14..0>\I AC6 AF4 3.3 V AE5 AD6 AF3 SRTS_STRB<2>\I AE4 ADAP_STRB<2>\I AD7 NCLK<2>\I RN157 AE6 3 6 4.7K AC7 CGC_SER_D<2>\I AF5 CGC_VALID<2>\I 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 14 13 12 11 10 3.3 V AAL1GATOR-32 PM73122 2 OF 5 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ALE WRB RDB CSB ACKB INTB TRSTB RSTB SYSCLK SCAN_MODEB TCLK TMS TDI TDO MICRO/JTAG AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AD12 AF11 AC12 AE11 AD11 AE10 AC5 AD4 B23 AC24 D22 A24 C23 A23 V23 V4 P23 N4 J4 J23 D23 D18 D14 D9 D4 C24 C3 B25 B2 AE25 AE2 AD24 AD3 AC23 AC18 AC13 AC9 AC4 A21 A10 P4 W4 AF6 AF17 AA26 L26 G23 U12 AAL1GATOR-32 PM73122 VDD23 3 OF 5 VSS27 VSS26 VDD22 VSS25 VDD21 VSS24 VDD20 VSS23 VDD19 VSS22 VDD18 VSS21 VDD17 VDD16 VSS20 VDD15 VSS19 VDD14 VSS18 VDD13 VSS17 VDD12 VSS16 VDD11 VSS15 VDD10 VSS14 VSS13 VDD9 VSS12 VDD8 VSS11 VDD7 VSS10 VDD6 VSS9 VDD5 VSS8 VDD4 VSS7 VDD3 VSS6 VDD2 VSS5 VDD1 VSS4 VDD0 VSS3 PCH_9 VSS2 PCH_8 VSS1 PCH_7 VSS0 PCH_6 PCH_5 PCH_4 PCH_3 PCH_2 PCH_1 POWER SUPPLY AF26 AF25 AF14 AF13 AF2 AF1 AE26 AE3 AE24 AE1 AD25 AD2 P26 P1 N26 N1 C25 C2 B26 B24 B3 B1 A26 A25 A14 A13 A2 A1 F 28F3> 14E9> 11F9> 29D9< 14E9> 11E9> 29D9< E 29C9< 29C9< 29B9> 29C4> 29C4> A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CGC_DOUT3 CGC_DOUT2 CGC_DOUT1 CGC_DOUT0 CGC_LINE4 CGC_LINE3 CGC_LINE2 CGC_LINE1 CGC_LINE0 SRTS_STBH ADAP_STBH NCLK TL_CLK_OE CGC_SER_D CGC_VALID 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 L_AD<31..0>\I 25G3<> 28C3<> 11F5<> 14F5<> 3B10<> 4D9<> 6D9<> 8D9<> 22C4<> 21D10<> F 3.3 V RN157 RN163 RN163 4 1 2 5 8 7 4.7K 4.7K 4.7K AAL3_ALE AAL_WRB AAL_RDB AAL3_CSB AAL3_ACKB AAL3_INTB 2 12 6 5 9 13 2 AAL_UP_CONTROL<13..0>\I 14E5<> 28E3<> 11F5<> 2.5 V 29B5<> 6C9< 21E6<> 22B8<> 3C10<> 4D9<> 14E5<> 11D5> 11E5<> 26C5> 28B3<> 8D9< 3E10> RSTB\I AAL_SYSCLK\I 0 1 E JTAG<2..0>\I TDO8 TDO9 D D C C 3.3 V 2.5 V 0.01UF C226 0.01UF C225 0.01UF C224 0.01UF C223 0.01UF C222 0.01UF C221 0.01UF C220 0.01UF C219 0.01UF C218 0.01UF C217 0.01UF C216 0.01UF 0.01UF 0.01UF 0.01UF C212 0.01UF C211 0.01UF C215 C214 C213 DECOUPLING CAPS ONE CAP PER TWO POWER PINS B DRAWING: AAL1GATOR_32_3.2 AAL3 Thu Nov 22 15:05:59 2001 B C210 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN AAL1GATOR-32_3 POWER AND UP ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:17 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE 3.3 V 0.01UF C232 0.01UF C231 0.01UF 0.01UF C229 0.01UF C228 0.01UF REV DESCRIPTION DATE APPR C230 AAL3_RAM1_D<15..0> 3.3 V 91 66 65 41 16 15 C227 H H 80MHZ U13 AAL3_RAM1_A<17..0> 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> 77 70 61 54 27 20 14 11 4 G G U12 AAL1GATOR-32 PM73122 4 OF 5 17A18 16C17 15B18 14A19 13D17 12C18 11B19 10A20 9 B20 8 A17 7 D19 6 C20 5 A22 4 D20 3 C21 2 B22 1 D21 0 C22 F RAM1_A17 RAM1_A16 RAM1_A15 RAM1_A14 RAM1_A13 RAM1_A12 RAM1_A11 RAM1_A10 RAM1_A9 RAM1_A8 RAM1_A7 RAM1_A6 RAM1_A5 RAM1_A4 RAM1_A3 RAM1_A2 RAM1_A1 RAM1_A0 4.7K 11D5> RAM1_CLK RAM INTERFACE E 3.3 V 4.7K R81 VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> RAM1_D15 RAM1_D14 RAM1_D13 RAM1_D12 RAM1_D11 RAM1_D10 RAM1_D9 RAM1_D8 RAM1_D7 RAM1_D6 RAM1_D5 RAM1_D4 RAM1_D3 RAM1_D2 RAM1_D1 RAM1_D0 RAM1_OEB RAM1_WEB1 RAM1_WEB0 RAM1_CSB RAM1_ADSCB RAM1_PAR1 RAM1_PAR0 SCAN_ENB A7 B8 C9 D10 B9 C10 A6 A11 B12 A12 D13 C13 B13 B14 C14 D15 A8 B16 D16 C19 B21 C16 B17 C12 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.3 V A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 1 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 CY71352 (256K X 18) F AAL3_RAM1_WE1B AAL3_RAM1_WE0B RN163 3 AAL3_RAM1_OEB AAL3_RAM1_CSB AAL3_RAM1_R/WB 6 4.7K 1 0 RN163 4 5 BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE E AAL3_RAM1_PAR<1..0> 3.3 V D 91 66 65 41 16 15 90 76 71 67 64 60 55 40 26 21 17 10 5 D 80MHZ U14 16H9> 77 70 61 54 27 20 14 11 4 VDD<6> VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> AAL3_RAM2_A<17..0> VDDQ<9> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> C 3.3 V 16F9> 16G9> 16G9> 16G9> 16F9> 11D5> 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 80 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 94 93 92 98 97 86 88 89 87 85 31 A<17> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> DP<1> DQ<15> DQ<14> DQ<13> DQ<12> DQ<11> DQ<10> DQ<9> DQ<8> DP<0> DQ<7> DQ<6> DQ<5> DQ<4> DQ<3> DQ<2> DQ<1> DQ<0> 24 23 22 19 18 13 12 9 8 74 73 72 69 68 63 62 59 58 1 15 14 13 12 11 10 9 8 0 7 6 5 4 3 2 1 0 AAL3_RAM2_PAR<1..0> AAL3_RAM2_D<15..0> 16F4<> 16H9<> C CY71352 (256K X 18) AAL3_RAM2_WE1B AAL3_RAM2_WE0B AAL3_RAM2_CSB RN164 AAL3_RAM2_OEB AAL3_RAM2_R/WB RAM2_CLK RN165 1 8 4 5 4.7K VSS<13> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> 4.7K BWS1 BWS0 CE3 CE1 CE2 OE WE CLK CEN ADV/LD MODE B B DRAWING: AAL1GATOR_32_3.3 AAL3 Thu Nov 22 15:06:01 2001 3.3 V 90 76 71 67 64 60 55 40 26 21 17 10 5 PMC-Sierra, Inc. 0.01UF C238 0.01UF C237 0.01UF 0.01UF C235 0.01UF C234 0.01UF C236 C233 A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 CES REF DESIGN AAL1GATOR-32_3 SRAM INTERFACE ENGINEER: BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:18 1 OF 29 A 10 9 8 7 6 5 4 3 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G 16C9<13C8< 10D8< U15 U15 WRDAT<15> WRDAT<14> WRDAT<13> WRDAT<12> WRDAT<11> WRDAT<10> WRDAT<9> WRDAT<8> WRDAT<7> WRDAT<6> WRDAT<5> WRDAT<4> WRDAT<3> WRDAT<2> WRDAT<1> WRDAT<0> WRADR<2> WRADR<1> WRADR<0> WRENB WRPA WRPRTY WRSOP WRSX AB2 AA3 Y4 AB1 AA2 Y3 AA1 Y2 W3 Y1 W2 V3 U4 W1 V2 U3 T1 R3 R2 T2 U1 U2 T4 V1 T3 AA25 Y23 AA24 AB25 AC26 AA23 AB24 AC25 AD26 AC24 AF24 AE23 AD22 AC21 AF23 AE22 AF20 AD19 AE20 AC20 AD21 AF21 AC19 AE21 4.7K AD20 R52 3 330 R82 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 G WRDAT<15..0>\I 22G9> ANYPHY_TDAT<15..0>\I WAN ANY-PHY/SCI-PHY RX R50 4.7K 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RN136 RN136 RN167 RN167 RN167 RN167 RN168 RN168 RN168 RN168 RN169 RN169 RN169 RN169 RN170 RN170 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 L24 L25 M23 L26 M24 M25 M26 N23 N24 N25 P25 P24 R26 R25 R24 T26 U24 V25 W26 U23 V24 W25 Y26 W24 Y25 AA26 W23 Y24 T24 R23 V26 T23 F 16C9<13C8<10C8< ANYPHY_TADR<3..0>\I 3 2 1 0 RN170 RN170 RN171 RN171 3 4 1 2 6 5 8 7 22 22 22 22 LTADR<11> LTADR<10> LTADR<9> LTADR<8> LTADR<7> LTADR<6> LTADR<5> LTADR<4> LTADR<3> LTADR<2> LTADR<1> LTADR<0> LTENB LTPA LTPRTY LTSOP LTSX LTCLK LOOP ANY-PHY TX RN172 RN172 RN172 2 3 4 7 6 5 4.7K 4.7K 4.7K WRENB\I WRPA\I 820 LTDAT<15> LTDAT<14> LTDAT<13> LTDAT<12> LTDAT<11> LTDAT<10> LTDAT<9> LTDAT<8> LTDAT<7> LTDAT<6> LTDAT<5> LTDAT<4> LTDAT<3> LTDAT<2> LTDAT<1> LTDAT<0> 3.3 V R53 F 22F9< 22F9> 22F9> 22F9> WRPRTY\I WRSOP\I 16B9< 13B8< 10B8< 16B9>13B8>10B8> 16B9<13B8<10B8< ANYPHY_TENB\I ANYPHY_TPA\I ANYPHY_TPAR\I E 16C9< 13C8< 10C8< 24E4> 22E3> ANYPHY_TSX\I LTCLK\I TDAT<15..0>\I 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 U25 T25 R1 P4 P3 P2 N2 N3 M1 M2 M3 L1 M4 L2 K1 L3 K2 J1 8 LOOP ANY-PHY/SCI-PHY RX D 22D3> 3.3 V TADR<4..0>\I 4 3 2 1 0 ----------LRDAT<15> LRDAT<14> LRDAT<13> LRDAT<12> LRDAT<11> LRDAT<10> LRDAT<9> LRDAT<8> LRDAT<7> LRDAT<6> LRDAT<5> LRDAT<4> LRDAT<3> LRDAT<2> LRDAT<1> LRDAT<0> LRADR<5> LRADR<4> LRADR<3> LRADR<2> LRADR<1> LRADR<0> LRENB LRPRTY LRPA LRSOP LRSX LRCLK WAN ANY-PHY/SCI-PHY TX WRCLK ----------WTDAT<15> WTDAT<14> WTDAT<13> WTDAT<12> WTDAT<11> WTDAT<10> WTDAT<9> WTDAT<8> WTDAT<7> WTDAT<6> WTDAT<5> WTDAT<4> WTDAT<3> WTDAT<2> WTDAT<1> WTDAT<0> WTADR<2> WTADR<1> WTADR<0> WTENB WTPA WTPRTY WTSOP WTSX WTCLK WRCLK\I 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 24E4> RN17 RN17 RN173 RN173 RN173 RN173 RN174 RN174 RN174 RN174 RN175 RN175 RN175 RN175 RN176 RN176 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 56 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2 1 0 WTDAT<15..0>\I 22F9< E RN176 3 RN176 4 RN177 1 RN177 7 2 56 RN177 6 56 820 R51 WTADR<2..0>\I 22E9< WTENB\I WTPA\I WTPRTY\I WTSOP\I 22D9< 22D9> 22E9< 22D9< D RN172 1 4.7K G1 H3 G2 F1 H4 G3 H2 H1 J3 J2 22D3> 22D3> 22D3<27E7> 22D3> TWRENB\I TPRTY\I TCA\I TSOC\I R83 330 PM7326 S/UNI-APEX WAN ANY-PHY/SCI-PHY 2 OF 5 K3 K4 C 24D4> LRCLK\I C 4.7K 820 R37 R38 PM7326 S/UNI-APEX LOOP ANY-PHY / SCI-PHY 1 OF 5 B DRAWING: APEX_1.1 APX Thu Nov 22 15:06:06 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN APEX-1.1 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:19 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE ISD<33..0> 3.3 V CBDQ<31..0> 0.01UF C294 0.01UF C296 0.01UF C298 0.01UF C308 0.01UF C310 0.01UF C312 REV DESCRIPTION DATE APPR H H 3E10> 21E6> JTAG<2..0>\I 0 TDO11 1 3.3 V U4 U3 U2 U5 R4 J6 J4 J2 C4 U7 U1 M7 M1 J7 J1 F7 F1 A7 A1 TCK TDI TMS TDO VDD5 VDD4 VDD3 VDD2 VDD1 VDDQ10 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 3.3 V 4.7K 4.7K 4.7K 4.7K 3.3 V G 3 9 43 49 1 14 27 U20 TSOP A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 35 22 34 33 32 31 30 29 26 25 24 23 11 10 9 8 7 6 5 4 3 2 1 0 RN86 RN86 RN86 RN86 U15 SBGA CMD<33> CMD<32> CMD<31> CMD<30> CMD<29> CMD<28> CMD<27> CMD<26> CMD<25> CMD<24> CMD<23> CMD<22> CMD<21> CMD<20> CMD<19> CMD<18> CMD<17> CMD<16> CMD<15> CMD<14> CMD<13> CMD<12> CMD<11> CMD<10> CMD<9> CMD<8> CMD<7> CMD<6> CMD<5> CMD<4> CMD<3> CMD<2> CMD<1> CMD<0> CMP<1> CMP<0> CMA<19> CMA<18> CMA<17> CMA<16> CMA<15> CMA<14> CMA<13> CMA<12> CMA<11> CMA<10> CMA<9> CMA<8> CMA<7> CMA<6> CMA<5> CMA<4> CMA<3> CMA<2> CMA<1> CMA<0> CMAB*<18> CMAB*<17> CMRWB CMCEB B13 B14 C14 A15 B15 C15 A16 D15 B16 C16 B17 D16 A18 C17 B18 A19 D17 C18 B19 A20 C19 B20 A21 D19 C20 B21 A22 C21 B22 A23 D21 C22 B23 A24 C23 D24 E24 F23 E25 E26 F25 G24 H23 F26 G25 H24 G26 H25 J24 K23 H26 J25 K24 J26 L23 K25 D26 F24 C26 RN62 1 1 D25 RN2 8 8 7 8 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6 G4 C6 B5 C5 R6 T5 T3 T2 A6 A5 A3 A2 C2 B3 C3 R2 N4 P4 E4 B2 B6 H4 K4 M4 R3 R5 J3 J5 R7 L5 G3 T7 B4 F4 D4 MT48LC4M16A2 F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 53 51 50 48 47 45 44 42 13 11 10 8 7 5 4 2 36 40 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 NC1 NC2 CKE CLK VSSQ1 VSSQ2 VSSQ3 VSSQ4 BA1 BA0 CS* WE* CAS* RAS* DQML 21 20 19 16 17 18 15 39 NC1 NC2 NC3 3.3 V 37 38 DQMH E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2 1 0 AD13 AF12 AE12 AD12 AF11 AC12 AE11 AD11 AE10 AC11 AF9 AD10 AE9 AF8 AC10 AD9 AE8 AF7 AD8 AE7 AF6 AC8 AD7 AE6 AC7 AD6 AE5 AF4 AC6 AD5 AE4 AF3 AE19 AD18 AC17 AF19 AE18 AD17 AF18 AC16 AE17 AD16 AE16 AC15 AE14 AE13 CBDQ<31> CBDQ<30> CBDQ<29> CBDQ<28> CBDQ<27> CBDQ<26> CBDQ<25> CBDQ<24> CBDQ<23> CBDQ<22> CBDQ<21> CBDQ<20> CBDQ<19> CBDQ<18> CBDQ<17> CBDQ<16> CBDQ<15> CBDQ<14> CBDQ<13> CBDQ<12> CBDQ<11> CBDQ<10> CBDQ<9> CBDQ<8> CBDQ<7> CBDQ<6> CBDQ<5> CBDQ<4> CBDQ<3> CBDQ<2> CBDQ<1> CBDQ<0> CBA<11> CBA<10> CBA<9> CBA<8> CBA<7> CBA<6> CBA<5> CBA<4> CBA<3> CBA<2> CBA<1> CBA<0> CBDQM<1> CBDQM<0> CBBS<1> CBBS<0> CBCSB CBWEB A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE1* CE2 CE3* W* CLK CKE* LBO* FT* DP QE* PE* BA* BB* ZZ ADV G* ZQ VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDD1 VDD2 VDD3 U10 PBGA DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 NC30 NC29 NC28 NC27 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 NC4 NC5 P2 N1 M2 L1 K2 H1 G2 E2 D1 D6 E7 F6 G7 H6 K7 L6 N6 P7 U6 T4 T1 R1 P6 P1 N7 N2 M6 L7 L4 L3 L2 K6 K1 H7 H2 G6 G5 A4 G1 F2 E6 E1 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 4.7K R342 G 8 7 6 3 1 2 4 5 3.3 V GS882Z18 1 MB ZBT SSRAM (512 K X 18) R338 4.7K 1 3 1 3 2 JP3 2 1 3 2 JP5 JP4 1 3 2 F JP7 B1 B7 C1 VSS1 VSS2 VSS3 P5 P3 N5 N3 M5 M3 K5 K3 H5 H3 F5 F3 E5 E3 D5 D3 C7 D2 D7 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 ZQ 6 12 46 52 28 41 54 E 19 ZBT_CLK TDO12\I 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 CMA<19..0> 3E10> 23E4< 21C5> CBA<11..0> VDD5 VDD4 VDD3 VDD2 VDD1 VDDQ10 VDDQ9 VDDQ8 VDDQ7 VDDQ6 VDDQ5 VDDQ4 VDDQ3 VDDQ2 VDDQ1 RN60 RN54 RN54 RN54 RN54 RN55 RN55 RN55 RN55 RN60 RN60 RN60 1 3 4 1 2 3 1 4 2 3 2 4 8 6 5 8 7 6 8 5 7 6 7 5 22 22 22 22 22 22 22 22 22 22 22 22 JTAG<2..0>\I U4 0 U3 U2 1 U5 R4 J6 J4 J2 C4 U7 U1 M7 M1 J7 J1 F7 F1 A7 A1 D 3.3 V RN62 2 RN61 1 RN61 2 RN61 3 3 9 43 49 1 14 27 7 8 7 6 5 5 6 22 22 22 22 22 22 22 AF16 AD15 AE15 AD14 AC14 AF15 4.7K 4.7K 4.7K 4.7K RN1 RN68 RN68 RN91 RN92 RN68 RN85 RN92 RN85 RN91 RN85 RN91 RN91 RN68 RN92 RN85 RN92 RN1 RN2 RN2 3 1 2 2 2 4 2 3 4 1 1 3 4 3 1 3 4 4 2 3 6 8 7 7 7 5 7 6 5 8 8 6 5 6 8 6 5 5 7 6 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3.3 V ZBT_CLK_INV MOTOROLA LW RAM TCK TDI TMS TDO 3.3 V 1 RN89 RN89 RN89 3 RN89 U21 TSOP A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 35 22 34 33 32 31 30 29 26 25 24 23 11 10 9 8 7 6 5 4 3 2 1 0 RN61 4 RN62 4 RN62 3 CBCASB CBRASB VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDD1 VDD2 VDD3 22 22 22 22 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6 G4 C6 B5 C5 R6 T5 T3 T2 A6 A5 A3 A2 C2 B3 C3 R2 N4 P4 E4 B2 B6 H4 K4 M4 R3 R5 J3 J5 R7 L5 G3 T7 B4 F4 D4 2 MT48LC4M16A2 C VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 4.7K R289 36 40 NC1 NC2 CKE CLK VSSQ1 VSSQ2 VSSQ3 VSSQ4 CAS* RAS* DQML VSS1 VSS2 VSS3 DQMH 17 18 15 39 B1 B7 C1 37 B 38 P5 P3 N5 N3 M5 M3 K5 K3 H5 H3 F5 F3 E5 E3 D5 D3 C7 D2 D7 3.3 V NC4 NC5 WE* 16 NC1 NC2 NC3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 53 51 50 48 47 45 44 42 13 11 10 8 7 5 4 2 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 PM7326 S/UNI-APEX SRAM INTERFACE 3 OF 5 RN1 RN1 2 1 4 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE1* CE2 CE3* W* CLK CKE* LBO* FT* DP QE* PE* BA* BB* ZZ ADV G* ZQ U11 PBGA DQ17 DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 NC30 NC29 NC28 NC27 NC26 NC25 NC24 NC23 NC22 NC21 NC20 NC19 NC18 NC17 NC16 NC15 NC14 NC13 NC12 NC11 NC10 NC9 NC8 NC7 P2 N1 M2 L1 K2 H1 G2 E2 D1 D6 E7 F6 G7 H6 K7 L6 N6 P7 U6 T4 T1 R1 P6 P1 N7 N2 M6 L7 L4 L3 L2 K6 K1 H7 H2 G6 G5 A4 G1 F2 E6 E1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4.7K R340 D 8 7 6 5 3.3 V GS882Z18 1 MB ZBT SSRAM (512 K X 18) 0 R341 R339 1 3 2 4.7K JP1 1 3 2 OPTIONAL CONNECTIONS SUPPORTING DIFFERENT TYPE OF RAMS C 3.3 V 4.7K R288 JP2 1 3 2 JP6 1 3 2 JP10 BA1 BA0 CS* 21 20 ZQ 19 ZQ B 6 12 46 52 28 41 54 3.3 V 0.01UF C295 0.01UF C297 0.01UF C307 0.01UF C309 0.01UF C311 0.01UF 3.3 V 3.3 V C313 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:20 2 1 OF 29 A 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF C282 C284 C286 C288 C290 C292 C283 C285 C287 C289 C291 A C293 21C5> SDRAM_CLK 0.01UF DECOUPLING FOR GS882Z18 1 CAP PER 2 POWER PINS DRAWING: TITLE=APEX_BLOCK ABBREV=APEX_BLOCK LAST_MODIFIED=Thu Nov 22 15:06:12 2001 5 4 3 DECOUPLING FOR MT48LC 1 CAP PER 2 POWER PINS TITLE: AAL1GATOR-32 REF DESIGN APEX-1.2 ENGINEER: BW 10 9 8 7 6 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G 3.3 V RN178 RN178 RN178 RN178 U15 CSB E1 F3 F2 E2 D1 F4 C4 D3 D2 E4 E3 C1 B12 AA4 AD23 AC22 AD4 AB3 AD1 0 AC2 1 AC3 2 AC1 4.7K R92 1 2 3 4 8 7 6 5 0.01UF C252 0.01UF C261 0.01UF C260 0.01UF C259 0.01UF C258 0.01UF C257 0.01UF C256 0.01UF C255 0.01UF C254 0.01UF 4.7K 4.7K 4.7K 4.7K 3.3 V U15 V23 V4 P23 N4 J23 J4 D23 D18 D14 D9 D4 C24 C3 B25 B2 AE25 AE2 AD24 AD3 AC23 AC18 AC13 AC9 AC4 D7 A10 A17 D20 G23 K26 U26 AB26 AF22 AF17 AF10 AF5 W4 R4 L4 G4 APEX_CSB APEX_WR APEX_ADSB APEX_BURSTB APEX_BLAST APEX_READYB APEX_INTHIB APEX_INTLOB APEX_WRDONEB APEX_BUSPOL APEX_BTERMB 1 2 0 4 3 5 8 9 7 10 6 APEX_UP_CONTROL<10..0>\I F WR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A3 B4 C5 D6 A4 B5 C6 A5 B6 C7 D8 A6 B7 C8 A7 B8 C9 D10 A8 B9 C10 A9 D11 B10 C11 B11 D12 A11 C12 A12 D13 C13 E 22C4<> 17F5<> 14F5<> 6D9<> 4D9<> 3B10<> 11F5<> 8D9<> 28C3<> 25G3<> L_AD<31..0>\I AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> ADSB BURSTB BLAST READYB INTHIB INTLOB WRDONEB BUSPOL BTERMB BCLK SYSCLK RSTB SCANEN SCANMB TDO TDI TCK TMS TRSTB OE 2.5 V BCLK\I VDD23 VDD22 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 VDD0 PCH16 PCH15 PCH14 PCH13 PCH12 PCH11 PCH10 PCH9 PCH8 PCH7 PCH6 PCH5 PCH4 PCH3 PCH2 PCH1 C253 10UF C262 F VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0 AF26 AF25 AF14 AF13 AF2 AF1 AE26 AE3 AE24 AE1 AD25 AD2 P26 P1 N26 N1 C25 C2 B26 B24 B3 B1 A26 A25 A14 A13 A2 A1 E 24D4> 0.01UF C242 0.01UF C250 0.01UF C249 0.01UF C248 0.01UF C247 0.01UF C246 0.01UF C245 0.01UF C244 0.01UF C251 0.01UF C243 10UF C241 RSTB\I 3.3 V TDO11 TDO10\I JTAG<2..0>\I 4.7K R88 26C5> 28B3<> 29B5<> 3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 22B8<> 6C9< 8D9< 20H4< 3E10> D PM7326 S/SUNI-APEX JTAG/MICRO 4 OF 5 PM7326 S/UNI-APEX POWER BLOCK 5 OF 5 D U16 13 56 12 10PF C263 3.3 V 50PPM 3.3V 80.000MHZ HCMOS Y1 8 ACT125 11 56 R89 R87 VDD OUT 5 1 56 R86 0.01UF 0.1UF C239 C240 4 GND NC/TS U16 10 9 ACT125 C 8 56 R90 ZBT_CLK 20E1< C U16 4 5 ACT125 6 56 R91 SDRAM_CLK 20A10< B DRAWING: APEX_1.3 APX Thu Nov 22 15:06:15 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN APEX-1.3 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:21 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H U25 19G3< U25 RDAT<15> RDAT<14> RDAT<13> RDAT<12> RDAT<11> RDAT<10> RDAT<9> RDAT<8> RDAT<7> RDAT<6> RDAT<5> RDAT<4> RDAT<3> RDAT<2> RDAT<1> RDAT<0> W1 W2 W3 Y1 Y2 W4 Y3 AA1 AA2 Y4 AA3 AB1 AB2 AA4 AB3 AC1 R3 T1 T2 T3 T4 V3 U1 U2 V2 R4 U4 4.7K R99 L2 G3 H4 G2 G1 H3 J4 H2 H1 J3 J2 J1 K3 L4 K2 K1 L3 P3 N1 N2 N3 M1 M4 M2 P2 N4 M3 4.7K R100 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WRDAT<15..0>\I INGRESS OUTPUT SLAVE INGRESS INPUT G MASTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RN171 RN171 RN179 RN179 RN179 RN179 RN180 RN180 RN180 RN180 RN181 RN181 RN181 RN181 RN182 RN182 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 330 AG31 AF29 AF30 AF31 AE29 AD28 AE30 AE31 AD29 AC28 AD30 AD31 AC29 AC30 AC31 AB29 Y28 AB31 AB30 AA28 ODAT<15> ODAT<14> ODAT<13> ODAT<12> ODAT<11> ODAT<10> ODAT<9> ODAT<8> ODAT<7> ODAT<6> ODAT<5> ODAT<4> ODAT<3> ODAT<2> ODAT<1> ODAT<0> ORDENB OCA OSOC OPRTY RDAT<15..0>\I 10D3> 13C3> 16C3> 27D7> G 19F3> 19F3< 19F3< 19F3< WRENB\I WRPA\I WRSOP\I RN182 3 RN182 4 6 5 8 WRPRTY\I RN183 1 RADDR<4>/RCA<3> RADDR<3>/RCA<2> RADDR<2>/RRDENB<4> RADDR<1>/RRDENB<3> RADDR<0>/RRDENB<2> RPRTY AA29 RN185 RN185 RN185 RN185 RN186 1 2 3 4 1 8 7 6 5 8 47 47 47 47 47 4 3 2 1 0 RADR<4..0>\I 10C3< 13C3< 16C3< 27C7< RPRTY\I RN186 7 47 RRDENB\I RCA\I RSOC\I 3.3 V 10B3> 13B3> 16B3> 27C7> 27C7< 10B3> 13B3> 16B3> 27B7> 27C7> F AA30 R101 OTSEN OFCLK RRDENB<1> RCA<1> U3 F --------------19E2> RFCLK RSOC RAVALID/RCA<4> WTDAT<15..0>\I E EGRESS OUTPUT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R21 R22 N28 M30 M31 N29 N30 N31 P29 R28 P30 R29 R30 R31 T28 T29 T30 T31 Y29 W28 Y30 Y31 W29 U29 W30 IDAT<15> IDAT<14> IDAT<13> IDAT<12> IDAT<11> IDAT<10> IDAT<9> IDAT<8> IDAT<7> IDAT<6> IDAT<5> IDAT<4> IDAT<3> IDAT<2> IDAT<1> IDAT<0> IFCLK V30 RPOLL --------------L1 EGRESS INPUT TFCLK TPOLL TDAT<15> TDAT<14> TDAT<13> TDAT<12> TDAT<11> TDAT<10> TDAT<9> TDAT<8> TDAT<7> TDAT<6> TDAT<5> TDAT<4> TDAT<3> TDAT<2> TDAT<1> TDAT<0> 19D2> WTADR<2..0>\I 19D3> 19D3> 19D3< 19D3> WTPRTY\I WTENB\I WTPA\I WTSOP\I 3.3 V 4.7K R20 2 IPRTY IWRENB<1> ICA<1> ISOC IAVALID/ICA<4> IPOLL PM7324 S/UNI-ATLAS SLAVE UTOPIA 2 OF 5 MASTER 330 330 2 1 0 IADDR<4>/ICA<3> IADDR<3>/ICA<2> IADDR<2>/IWRENB<4> IADDR<1>/IWRENB<3> IADDR<0>/IWRENB<2> RN186 RN186 RN187 RN187 RN187 RN187 RN188 RN188 RN188 RN188 RN189 RN189 RN189 RN189 RN190 RN190 RN190 RN190 RN191 RN191 RN191 RN191 RN192 RN192 RN192 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 47 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 3 2 1 0 TDAT<15..0>\I 19E9< 27G7< SLAVE E RN183 7 22 4.7K R103 W31 U28 AA31 V29 TADDR<4>/TCA<3> TADDR<3>/TCA<2> TADDR<2>/TWRENB<4> TADDR<1>/TWRENB<3> TADDR<0>/TWRENB<2> TPRTY TWRENB<1> TAVALID/TCA<4> TCA<1> TSOC PM7324 S/UNI-ATLAS MASTER UTOPIA 1 OF 5 TADR<4..0>\I 19D9< 27F7< TPRTY\I TWRENB\I TCA\I TSOC\I 19C9< 27F7< 19D9< 27F7< 19C9> 27E7> 19C9< 27F7< D D 6 24E4> OFCLK\I 24E4> RFCLK\I C C U25 11 10 9 8 7 6 5 4 3 2 1 0 0 1 3 2 C23 B23 A23 C22 D21 B22 A22 C21 D20 B21 A21 C20 A24 C24 B24 D23 A25 AK22 B 28F3> 28F3<> 26C5> 17E6<> 11E5<> 3C10<> 4D9<> 14E5<> 21E6<> 28B3<> 29B5<> 6C9< 8D9< CHIP_ADDRESS<19..0>\I ATLAS_UP_CONTROL<5..0>\I A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> ALE CSB RDB WRB RSTB HALFSECCLK RSTB\I D<15> D<14> D<13> D<12> D<11> D<10> D<9> D<8> D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> INTB IDREQ EDREQ BUSYB J31 15 J30 14 J29 13 H31 12 H30 11 J28 10 H29 9 G31 8 G30 7 H28 6 G29 5 F31 4 F30 3 F29 2 E31 1 E30 0 K31 K30 L28 K29 L_AD<31..0>\I 3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 14F5<> 17F5<> 25G3<> 28C3<> 21D10<> 3.3 V B RN184 RN184 5 4 1 2 4.7K 8 7 4.7K DRAWING: ATLAS_1.1 ATLAS1 Thu Nov 22 15:06:18 2001 PM7324 S/UNI-ATLAS MICRO INTERFACE 3 OF 5 PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: ISSUE DATE: JAN 2001 A TITLE: AAL1GATOR-32 REF DESIGN REVISION NUMBER: ATLAS INGRESS AND EGRESS INTERFACE 3.0 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 PAGE:22 1 OF 29 10 9 8 7 6 5 4 3 2 1 SRAM DECOUPLING CAPS 3.3 V 1 PIN PER 2 POWER PINS U25 C327 REVISIONS ZONE REV DESCRIPTION DATE APPR 0.01UF C303 0.01UF C304 0.01UF C305 0.01UF C306 0.01UF C314 0.01UF C315 0.01UF C316 0.01UF C317 0.01UF C318 0.01UF C319 0.01UF C320 0.01UF C321 0.01UF C322 0.01UF C323 0.01UF C324 0.01UF C325 0.01UF C326 0.01UF H H ISD<63> ISD<62> ISD<61> ISD<60> ISD<59> ISD<58> ISD<57> ISD<56> ISD<55> ISD<54> ISD<53> ISD<52> ISD<51> ISD<50> ISD<49> ISD<48> ISD<47> ISD<46> ISD<45> ISD<44> ISD<43> ISD<42> ISD<41> ISD<40> ISD<39> ISD<38> ISD<37> ISD<36> ISD<35> ISD<34> ISD<33> ISD<32> ISD<31> ISD<30> ISD<29> ISD<28> ISD<27> ISD<26> ISD<25> ISD<24> ISD<23> ISD<22> ISD<21> ISD<20> ISD<19> ISD<18> ISD<17> ISD<16> ISD<15> ISD<14> ISD<13> ISD<12> ISD<11> ISD<10> ISD<9> ISD<8> ISD<7> ISD<6> ISD<5> ISD<4> ISD<3> ISD<2> ISD<1> ISD<0> ISA<19> ISA<18> ISA<17> ISA<16> ISA<15> ISA<14> ISA<13> ISA<12> ISA<11> ISA<10> ISA<9> ISA<8> ISA<7> ISA<6> ISA<5> ISA<4> ISA<3> ISA<2> ISA<1> ISA<0> ISP<7> ISP<6> ISP<5> ISP<4> ISP<3> ISP<2> ISP<1> ISP<0> ISADSB ISRWB ISOEB AG1 AG2 AF4 AG3 AH1 AJ5 AH6 AK5 AL5 AJ6 AK6 AL6 AJ7 AH8 AK7 AL7 AJ8 AH9 AK8 AL8 AJ9 AK9 AL9 AJ10 AH11 AK10 AL10 AJ11 AH12 AK11 AL11 AJ12 AH13 AK12 AL12 AJ13 AK13 AL13 AJ14 AK14 AH15 AJ15 AL16 AK16 AJ16 AH16 AL17 AK17 AJ17 AK18 AH17 AJ18 AL19 AK19 AJ19 AL20 AK20 AH19 AJ20 AL21 AK21 AH20 AJ21 AL22 AJ23 AL24 AK24 AH23 AJ24 AL25 AK25 AH24 AJ25 AL26 AK26 AJ26 AL27 AK27 AH26 AJ27 AH31 AG29 AF28 AG30 AD3 AE1 AE2 AD4 AE3 AF1 AF2 AF3 AK23 AJ22 AL23 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 4 1 2 3 ISD<63..0> 3.3 V 3.3 V ISA<19..0> 50 16 49 15 48 14 47 13 46 12 45 11 44 10 81 9 82 8 99 7 100 6 32 5 33 4 34 3 35 2 36 1 37 0 93 94 95 96 98 97 92 86 88 89 87 85 14 64 31 66 38 39 42 43 U27 VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> 16 91 65 41 15 77 70 61 54 27 20 11 4 U26 50 49 48 47 46 45 44 81 82 99 100 32 33 34 35 36 37 93 94 95 96 98 97 92 86 88 89 87 85 14 64 31 66 38 39 42 43 G 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> BA BB BC BD CE1 CE2 CE3 G W CK CKE ADV FT ZZ LBO QE GS841Z36T (256K X 36) F 3.3 V 4.7K R23 4.7K R24 1 20E3> TDO12\I 0 VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> 3E10< TDO13\I 0 E 3 2 1 0 D19 B20 A20 C19 3.3 V U28 50 16 49 15 48 14 47 13 46 12 45 11 44 10 81 9 82 8 99 7 100 6 32 5 33 4 34 3 35 2 36 1 37 0 93 94 95 96 98 97 92 86 88 89 87 85 14 64 31 66 38 39 42 43 90 76 71 67 60 55 40 26 21 17 10 5 ESP<3> ESP<2> ESP<1> ESP<0> 90 76 71 67 60 55 40 26 21 17 10 5 TMS TDI TDO TCK ESP<3..0> VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1> DQC<9> DQC<8> DQC<7> DQC<6> DQC<5> DQC<4> DQC<3> DQC<2> DQC<1> DQD<9> DQD<8> DQD<7> DQD<6> DQD<5> DQD<4> DQD<3> DQD<2> DQD<1> 51 31 52 30 53 29 56 28 57 27 58 26 59 25 62 24 63 23 80 22 79 21 78 20 75 19 74 18 73 17 72 16 69 15 68 14 1 13 2 12 3 11 6 10 79 88 97 12 6 13 5 30 4 29 3 28 2 25 1 24 0 23 3 22 2 19 1 18 0 ESD<31..0> 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 B19 A19 C18 B18 D17 C17 A16 B16 C16 D16 A15 B15 C15 B14 D15 C14 A13 B13 C13 A12 B12 D13 C12 A11 B11 D12 C11 A10 B10 D11 C10 A9 ESD<31> ESD<30> ESD<29> ESD<28> ESD<27> ESD<26> ESD<25> ESD<24> ESD<23> ESD<22> ESD<21> ESD<20> ESD<19> ESD<18> ESD<17> ESD<16> ESD<15> ESD<14> ESD<13> ESD<12> ESD<11> ESD<10> ESD<9> ESD<8> ESD<7> ESD<6> ESD<5> ESD<4> ESD<3> ESD<2> ESD<1> ESD<0> A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> BA BB BC BD CE1 CE2 CE3 G W CK CKE ADV FT ZZ LBO QE TMS TDI TDO TCK GS841Z36T (256K X 36) 3.3 V 4.7K R25 4.7K R26 1 DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1> DQC<9> DQC<8> DQC<7> DQC<6> DQC<5> DQC<4> DQC<3> DQC<2> DQC<1> DQD<9> DQD<8> DQD<7> DQD<6> DQD<5> DQD<4> DQD<3> DQD<2> DQD<1> 51 52 53 56 57 58 59 62 63 80 79 78 75 74 73 72 69 68 1 2 3 6 7 8 9 12 13 30 29 28 25 24 23 22 19 18 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> 16 91 65 41 15 77 70 61 54 27 20 11 4 G F E 16 91 65 41 15 77 70 61 54 27 20 11 4 VDD<5> VDD<4> VDD<3> VDD<2> VDD<1> VDDQ<8> VDDQ<7> VDDQ<6> VDDQ<5> VDDQ<4> VDDQ<3> VDDQ<2> VDDQ<1> ESA<19..0> 16 15 14 13 RN183 RN183 RN193 RN193 RN193 RN193 RN194 RN194 RN194 RN194 RN195 RN195 RN195 RN195 RN196 RN196 RN196 3 4 1 2 6 5 8 7 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 22 D 12 11 10 9 8 7 6 5 4 3 2 1 0 3 4 1 2 3 4 1 2 3 4 1 2 3 6 5 8 7 6 5 8 7 6 5 8 7 6 D9 C8 A7 B7 D8 C7 A6 B6 C6 A5 B5 D6 D1 E3 F4 E2 E1 F3 F2 F1 ESA<19> ESA<18> ESA<17> ESA<16> ESA<15> ESA<14> ESA<13> ESA<12> ESA<11> ESA<10> ESA<9> ESA<8> ESA<7> ESA<6> ESA<5> ESA<4> ESA<3> ESA<2> ESA<1> ESA<0> RN196 5 RN197 22 8 RN197 7 22 RN197 6 22 22 RN197 5 RN198 8 22 RN198 7 22 RN198 6 22 RN198 5 22 RN199 8 22 RN199 7 22 RN199 6 22 RN199 5 22 RN200 8 22 RN200 7 22 RN200 6 22 RN200 5 22 22 7 6 5 4 3 2 1 0 16 15 14 13 4 1 2 3 4 1 2 3 4 1 2 3 4 12 11 10 9 8 7 6 5 4 3 2 1 0 A<16> A<15> A<14> A<13> A<12> A<11> A<10> A<9> A<8> A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0> BA BB BC BD CE1 CE2 CE3 G W CK CKE ADV FT ZZ LBO QE GS841Z36T (256K X 36) 3.3 V 4.7K R27 ESOEB ESRWB ESADSB A8 C9 B8 ESOEB ESRWB ESADSB ISADSB ISRWB ISOEB 1 0 4.7K R28 C ISP<7..0> B9 ESYSCLK ISYSCLK TDO TDI TCK TMS TRSTB AH21 M28 L31 L30 M29 L29 B25 0.1UF C278 3.3 V B U16 1 U25 POWER BLOCK PM7324 5 OF 5 0 1 2 330 R15 90 76 71 67 60 55 40 26 21 17 10 5 VSS<12> VSS<11> VSS<10> VSS<9> VSS<8> VSS<7> VSS<6> VSS<5> VSS<4> VSS<3> VSS<2> VSS<1> PM7324 S/UNI-ATLAS SRAM INTERFACE 4 OF 5 TMS TDI TDO TCK DQA<9> DQA<8> DQA<7> DQA<6> DQA<5> DQA<4> DQA<3> DQA<2> DQA<1> DQB<9> DQB<8> DQB<7> DQB<6> DQB<5> DQB<4> DQB<3> DQB<2> DQB<1> DQC<9> DQC<8> DQC<7> DQC<6> DQC<5> DQC<4> DQC<3> DQC<2> DQC<1> DQD<9> DQD<8> DQD<7> DQD<6> DQD<5> DQD<4> DQD<3> DQD<2> DQD<1> 51 52 53 56 57 58 59 62 63 80 79 78 75 74 73 72 69 68 1 2 3 6 7 8 9 12 13 30 29 28 25 24 23 22 19 18 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 4 5 6 7 D C JTAG<2..0>\I VCC 3E10> B DRAWING: ATLAS_1.2 ATLAS Thu Nov 22 15:06:24 2001 VDD<40-1> VBIAS GND<48-1> 3 56 R12 3.3 V 50PPM 3.3V 50.000MHZ HCMOS U22 8 2 ACT125 ESYSCLK C209 0.01UF 0.1UF VDD OUT 5 1 56 R11 2 C264 4 U43 1 ACT125 56 3 R14 GND NC/TS ISYSCLK 3.3 V PMC-Sierra, Inc. C267 0.01UF C268 0.01UF C269 0.01UF C270 0.01UF C271 0.01UF C272 0.01UF C273 0.01UF C274 0.01UF C275 0.01UF C276 0.01UF C277 0.01UF C279 0.01UF C280 0.01UF C281 0.01UF C299 0.01UF C300 0.01UF C301 0.01UF A 0.01UF C265 0.01UF C266 0.01UF C302 DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN ATLAS-SSRAM INTERFACE ENGINEER: BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:23 1 OF 29 A SUNI-ATLAS DECOUPLING CAPS 1 PIN PER 2 POWER PINS 10 9 8 7 6 5 4 3 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H J2 TX RECEPTACLE_RA 1 2 3 4 5 6 7 8 G AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PRTY SOC LENB A0 A1 A2 A3 A4 CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT EBBI80 22E3> TDAT<15..0>\I F 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 22D3> 22D3> 22D3> 22D3> TPRTY\I TSOC\I TWRENB\I TADR<4..0>\I 0 1 2 3 4 28 29 30 31 32 33 34 35 36 37 38 39 40 22D3< 19C9> TCA\I E GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 G F E UTOPIA2 INTERFACE J4 RX RECEPTACLE_RA 1 2 3 4 5 6 7 8 D AUX0 AUX1 AUX2 AUX3 AUX4 AUX5 AUX6 AUX7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 PRTY SOC LENB A0 A1 A2 A3 A4 CLAV0 CLAV1 CLAV2 CLAV3 CLKIO EXTREF TRG_IN TRG_OUT EBBI80 22G3< 16C3> 13C3> 10D3> RDAT<15..0>\I C 22F3< 16B3> 13B3> 10B3> 22F3< 16B3< 13B3< 10B3< 22F3> 22F3> 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 RPRTY\I RSOC\I RRDENB\I RADR<4..0>\I 0 1 2 3 4 28 29 30 31 32 33 34 35 36 37 38 39 40 22F3< 16B3> 13B3> 10B3> RCA\I GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 D C B B DRAWING: ATLAS_1.6 ATLAS Thu Nov 22 15:05:15 2001 UTOPIA2 INTERFACE PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESGIN UTOPIA CONNECTOR ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:24 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G F F 3.3 V 4 8 15 20 E 3.3 V 50PPM 3.3V 25.000MHZ HCMOS Y3 8 0.1UF C399 4 E U61 VDD OUT 5 1 56 R111 PI49FCT3807 VCC VCC VCC VCC 1 A GND NC/TS B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 3 5 7 9 11 12 14 16 18 19 RN15 RN15 RN15 RN15 RN16 RN16 RN16 RN16 RN17 RN17 1 2 3 4 1 2 3 4 1 2 8 7 6 5 8 7 6 5 8 7 56 56 56 56 56 56 56 56 56 56 WRCLK\I RFCLK\I OFCLK\I LTCLK\I LRCLK\I RPHY_CLK\I TPHY_CLK\I LCLK\I LCLK_CPLD\I BCLK\I 19E3< 22C7< 22D7< 19E9< 19C9< 10B3< 13B3< 16B3< 10B3< 13B3< 16B3< 25E2< 28B3< 29B5< 21E6< D 2 6 10 13 17 GND GND GND GND GND D 3.3 V C 0.01UF 0.01UF 0.01UF 0.01UF C403 C402 C401 C400 C DECOUPLING CAPS B DRAWING: OSCIALLTOE_25M OSCILLATOR_25M Thu Nov 22 15:05:08 2001 B PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN 25MHZ OSCILLATOR BLOCK ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:25 1 OF 29 A 10 9 8 7 6 3.3 V 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR C419 0.01UF C418 0.01UF C417 0.01UF C416 0.01UF C415 0.01UF C414 0.01UF C413 C421 0.01UF C420 0.01UF 0.1UF H H 7E9< 5E9< 9E9< XCLK\I 50PPM 3.3V 51.840MHZ Y4 HCMOS 8 4 3.3 V G 0.01UF 0.1UF C422 C423 VDD OUT 5 1 GND NC/TS 50PPM 3.3V 19.440MHZ HCMOS VDD OUT U47 XC95288XL-PQ208 CPLD 1 OF 2 8 9 10 11 12 13 14 15 16 17 18 19 2 13 24 27 42 52 68 81 93 104 108 129 130 141 156 163 177 190 207 U47 XC95288XL-PQ208 CPLD 2 OF 2 GND_1 VCCINT_1 GND_2 VCCINT_2 GND_3 VCCINT_3 GND_4 VCCINT_4 GND_5 VCCINT_5 GND_6 GND_7 VCCIO_1 GND_8 VCCIO_2 GND_9 VCCIO_3 VCCIO_4 GND_10 GND_11 VCCIO_5 GND_12 VCCIO_6 GND_13 VCCIO_7 GND_14 VCCIO_8 GND_15 VCCIO_9 GND_16 VCCIO_10 GND_17 VCCIO_11 GND_18 VCCIO_12 GND_19 POWER 3.3 V 11 59 124 153 204 1 26 53 65 79 92 105 132 157 172 181 184 G 3.3 V Y5 8 0.01UF 0.1UF C424 C425 4 5 1 GND NC/TS 32PPM 3.3V 37.056MHZ HCMOS VDD OUT F RN4 RN4 RN4 RN4 RN5 RN5 RN5 RN5 RN6 RN6 RN6 RN6 RN3 RN3 RN3 1 2 3 1 1 2 3 4 1 2 3 4 1 2 3 4 RES_ARRAY_4 8 7 6 5 8 7 6 5 8 7 6 5 7 6 5 RES_ARRAY_4 56 56 56 56 56 56 56 56 56 56 56 56 22 22 22 143 142 140 139 138 137 136 135 134 133 131 155 154 152 151 150 149 148 147 146 145 144 169 168 167 166 165 164 162 161 160 159 158 IO16<11> IO16<10> IO16<9> IO16<8> IO16<7> IO16<6> IO16<5> IO16<4> IO16<3> IO16<2> IO16<1> IO14<11> IO14<10> IO14<9> IO14<8> IO14<7> IO14<6> IO14<5> IO14<4> IO14<3> IO14<2> IO14<1> IO12<11> IO12<10> IO12<9> IO12<8> IO12<7> IO12<6> IO12<5> IO12<4> IO12<3> IO12<2> IO12<1> IO10<11> IO10<10> IO10<9> IO10<8> IO10<7> IO10<6> IO10<5> IO10<4> IO10<3> IO10<2> IO10<1> IO8<10> IO8<9> IO8<8> IO8<7> IO8<6> IO8<5> IO8<4> IO8<3> IO8<2> IO8<1> IO6<9> IO6<8> IO6<7> IO6<6> IO6<5> IO6<4> IO6<3> IO6<2> IO6<1> IO4<6> IO4<5> IO4<4> IO4<3> IO4<2> IO4<1> IO2<10> IO2<9> IO2<8> IO2<7> IO2<6> IO2<5> IO2<4> IO2<3> IO2<2> IO2<1> IO/GTS<4> IO/GTS<3> IO/GTS<2> IO/GTS<1> IO15<11> IO15<10> IO15<9> IO15<8> IO15<7> IO15<6> IO15<5> IO15<4> IO15<3> IO15<2> IO15<1> IO13<11> IO13<10> IO13<9> IO13<8> IO13<7> IO13<6> IO13<5> IO13<4> IO13<3> IO13<2> IO13<1> IO11<11> IO11<10> IO11<9> IO11<8> IO11<7> IO11<6> IO11<5> IO11<4> IO11<3> IO11<2> IO11<1> IO9<11> IO9<10> IO9<9> IO9<8> IO9<7> IO9<6> IO9<5> IO9<4> IO9<3> IO9<2> IO9<1> IO7<10> IO7<9> IO7<8> IO7<7> IO7<6> IO7<5> IO7<4> IO7<3> IO7<2> IO7<1> IO5<9> IO5<8> IO5<7> IO5<6> IO5<5> IO5<4> IO5<3> IO5<2> IO5<1> IO3<8> IO3<7> IO3<6> IO3<5> IO3<4> IO3<3> IO3<2> IO3<1> IO1<10> IO1<9> IO1<8> IO1<7> IO1<6> IO1<5> IO1<4> IO1<3> IO1<2> IO1<1> IO/GCK<3> IO/GCK<2> IO/GCK<1> IO/GSR TCK TDI TDO TMS IOBLOCK 128 127 126 125 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 107 106 103 102 101 100 99 97 95 91 90 89 88 87 86 85 84 83 82 80 78 77 76 75 74 73 72 71 70 69 67 66 64 63 62 61 60 58 57 56 54 51 50 49 48 47 45 43 41 40 39 38 37 36 35 34 33 32 31 30 29 28 55 46 44 206 98 94 176 96 RN11 RN11 RN11 RN11 RN12 RN12 RN12 RN12 1 2 3 4 1 2 3 4 RES_ARRAY_4 8 7 6 5 8 7 6 5 56 56 56 56 56 56 56 56 7 6 5 4 3 2 1 0 CHIP_ADDRESS<19..0>\I LREFCLK\I C1FP\I LAC1\I SS1_DFP\I ATLAS_UP_CONTROL<5..0>\I 3B10< 4D9< 6D9< 8D9< 11G9< 14F9< 17E9< 22B8< 4F9< 6F9< 8F9< 5F3< 7F3< 9F3< 10F3<13F4<16F4< 4F9< 6F9< 8F9< 3E10< 22B8<> F Y6 8 4 5 1 3.3 V 16E4<13E4<10E4< C426 0.01UF 0.1UF C427 GND NC/TS 2 3 4 ATLAS_INTB ATLAS_BUSYB ATLAS_RDB ATLAS_WRB ATLAS_CSB ATLAS_ALE 5 4 3 2 1 0 ADETECT<3..1>\I AACTIVE<3..1>\I 16F9> 13F9> 10F9> SREFCLK\I FASTCLK\I CLK52M\I SS0_DCK\I SS13_ACK\I RN7 RN7 RN7 RN7 RN8 RN8 RN8 RN8 1 2 3 4 1 2 3 4 RES_ARRAY_4 5F3< 7F3< 9F3< 10D3<13D4<16D4< 10D9< 13D9< 16D9< 5F9< 7F9< 9F9< 3E10< 3D10< 11F5<> 14E5<> 17E6<> 21F6<> APEX_UP_CONTROL<10..0>\I E 3.3 V D13 270 R16 2 1 11 HCT 125 HCT541 AAL1GATOR_32 INTERRUPT LEDS 2 1 D22 D20 D18 D21 D19 D17 D16 D15 U23 12 2 3 10 APEX_BUSPOL 9 APEX_INTLOB 8 APEX_INTHIB 7 APEX_WRDONEB 6 APEX_BTERMB 5 APEX_READYB 4 APEX_BURSTB 3 APEX_BLAST 2 APEX_WR 1 0 4 3 2 1 0 8 7 6 5 8 7 6 5 56 56 56 56 56 56 56 56 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10 9 8 7 6 5 4 3 2 1 0 AAL_UP_CONTROL<13..0>\I 3.3 V E U24 ATLAS INTERRUPT LED 9 8 7 6 5 4 3 2 A7 A6 A5 A4 A3 A2 A1 A0 OE1 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 OE2 11 12 13 14 15 16 17 18 1 2 2 2 2 2 2 2 2 RN13 RN13 RN13 RN13 RN14 RN14 RN14 1 2 3 4 1 2 3 8 7 6 5 8 7 6 5 270 270 270 270 270 270 270 270 D AAL1_3 AAL1_2 AAL1_1 1 1 1 YELLOW APEX INTERRUPT LEDS D14 270 R17 2 1 8 13 3C10<> SPECTRA_UP_CONTROL<4..0>\I U23 HCT 125 9 APEX_CSB 185 APEX_ADSB 183 SPECTRA_WRB/RWB 182 SPECTRA_RDB/E 180 SPECTRA_CSB 179 SPECTRA_ALE 178 SPECTRA_INTB 175 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 174 173 171 170 196 195 194 193 192 191 189 188 187 186 208 205 203 202 201 200 199 198 197 AAL3_INTB AAL2_INTB AAL1_INTB TE3_INTB TE2_INTB TE1_INTB RN9 RN9 RN9 RN9 RN10 RN10 RN10 RN10 1 2 3 4 1 2 3 4 RES_ARRAY_4 TEMUX_UP_CONTROL<10..0>\I 4E9<> 6E9<> 8E9<> 0 10 TEMUX_3 1 TEMUX_2 1 TEMUX_1 1 1 3C1< 3D1< TRCLK\I RRCLK\I RN2 RN3 4 1 RES_ARRAY_4 5 8 22 22 8 7 6 5 8 7 6 5 56 56 56 56 56 56 56 56 TEMUX INTERRUPT LEDS 9 8 10 D RN14 4 SPECTRA INTERRUPT LED YELLOW LEDS 1 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 L_AD<31..0>\I 3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 14F5<> 17F5<> 21D10<> 22C4<> 25G3<> C 7 6 5 4 3 2 8 7 6 5 4 3 2 1 0 0 1 14 12 10 8 6 4 25 23 22 21 20 19 18 17 16 15 5 3 9 7 19 C 25C2> LA<28..2>\I 25C1> UP_CONTROL<8..0>\I LBE<1..0>\I L_INTB\I L_BTERMB\I L_BLASTB L_LW/RB L_READYB L_LSERRB L_ADSB L_WAITB L_DT_RB L_DENB L_ALE LBE0 LBE1 B 25C2> 25E2< 25F2< B 1 0 56 1 3 5 7 1 2 3 4 R118 LCLK_CPLD\I RSTB\I J6 2 4 6 8 3.3 V 24D4> 29B5<> 6C9< 8D9< 3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 21E6<> 22B8<> 26C5> 8 7 6 5 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: DRAWING: TITLE: AAL1GATOR-32 REF DESIGN CPLD_1 BLOCK CPLD_1 BLOCK CPL1 Thu Nov 22 15:05:04 2001 ENGINEER: 3 BW 2 REVISION NUMBER: 3.0 PAGE:26 1 OF 29 ISSUE DATE: JAN 2001 A 4.7K RN124 A 10 9 8 7 6 5 4 10 9 8 7 6 3.3 V 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR C440 0.01UF C439 0.01UF C438 0.01UF C437 0.01UF C436 0.01UF C435 0.01UF C434 0.01UF C442 0.01UF 0.1UF C441 H H G 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 143 142 140 139 138 137 136 135 134 133 131 155 154 152 151 150 149 148 147 146 145 144 169 168 167 166 165 164 162 161 160 159 158 185 183 182 180 179 178 175 174 173 171 170 196 195 194 193 192 191 189 188 187 186 208 205 203 202 201 200 199 198 197 U65 XC95288XL-PQ208 CPLD 1 OF 2 IO16<11> IO16<10> IO16<9> IO16<8> IO16<7> IO16<6> IO16<5> IO16<4> IO16<3> IO16<2> IO16<1> IO14<11> IO14<10> IO14<9> IO14<8> IO14<7> IO14<6> IO14<5> IO14<4> IO14<3> IO14<2> IO14<1> IO12<11> IO12<10> IO12<9> IO12<8> IO12<7> IO12<6> IO12<5> IO12<4> IO12<3> IO12<2> IO12<1> IO10<11> IO10<10> IO10<9> IO10<8> IO10<7> IO10<6> IO10<5> IO10<4> IO10<3> IO10<2> IO10<1> IO8<10> IO8<9> IO8<8> IO8<7> IO8<6> IO8<5> IO8<4> IO8<3> IO8<2> IO8<1> IO6<9> IO6<8> IO6<7> IO6<6> IO6<5> IO6<4> IO6<3> IO6<2> IO6<1> IO15<11> IO15<10> IO15<9> IO15<8> IO15<7> IO15<6> IO15<5> IO15<4> IO15<3> IO15<2> IO15<1> IO13<11> IO13<10> IO13<9> IO13<8> IO13<7> IO13<6> IO13<5> IO13<4> IO13<3> IO13<2> IO13<1> IO11<11> IO11<10> IO11<9> IO11<8> IO11<7> IO11<6> IO11<5> IO11<4> IO11<3> IO11<2> IO11<1> IO9<11> IO9<10> IO9<9> IO9<8> IO9<7> IO9<6> IO9<5> IO9<4> IO9<3> IO9<2> IO9<1> IO7<10> IO7<9> IO7<8> IO7<7> IO7<6> IO7<5> IO7<4> IO7<3> IO7<2> IO7<1> IO5<9> IO5<8> IO5<7> IO5<6> IO5<5> IO5<4> IO5<3> IO5<2> IO5<1> IO3<8> IO3<7> IO3<6> IO3<5> IO3<4> IO3<3> IO3<2> IO3<1> IO1<10> IO1<9> IO1<8> IO1<7> IO1<6> IO1<5> IO1<4> IO1<3> IO1<2> IO1<1> IO/GCK<3> IO/GCK<2> IO/GCK<1> IO/GSR TCK TDI TDO TMS 128 127 126 125 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 107 106 103 102 101 100 99 97 95 91 90 89 88 87 86 85 84 83 82 80 78 77 76 75 74 73 72 71 70 69 67 66 64 63 62 61 60 58 57 56 54 51 50 49 48 47 45 43 41 40 39 38 37 36 35 34 33 32 31 30 29 28 55 46 44 206 98 94 176 96 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 ATM NETWORK CLK FOR DS3 SRTS IMPLEMENTED IN CPLD J1 202P 5 2 3 2 13 24 27 42 52 68 81 93 104 108 129 130 141 156 163 177 190 207 U65 XC95288XL-PQ208 CPLD 2 OF 2 GND_1 VCCINT_1 VCCINT_2 GND_2 VCCINT_3 GND_3 VCCINT_4 GND_4 VCCINT_5 GND_5 GND_6 GND_7 VCCIO_1 GND_8 VCCIO_2 GND_9 VCCIO_3 GND_10 VCCIO_4 GND_11 VCCIO_5 GND_12 VCCIO_6 GND_13 VCCIO_7 GND_14 VCCIO_8 GND_15 VCCIO_9 GND_16 VCCIO_10 GND_17 VCCIO_11 GND_18 VCCIO_12 GND_19 POWER 3.3 V 11 59 124 153 204 1 26 53 65 79 92 105 132 157 172 181 184 G F SMB 4 1 F 3.3 V 50PPM 3.3V 2.048MHZ HCMOS Y11 C444 8 4 0.01UF 0.1UF C445 VDD OUT 5 1 22 R19 GND NC/TS E 3.3 V 50PPM 3.3V 1.544MHZ Y10 HCMOS 8 4 E C443 0.01UF 0.1UF C446 VDD OUT 5 1 22 R18 GND NC/TS NETWORK_CLK 5C8> 17E9> 14E9> 11E9> RECVCLK1\I CGC_LINES<14..0>\I 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 D 8 7 6 5 4 3 2 1 0 1 0 5 4 3 2 1 0 2 1 0 2 1 0 0 1 2 0 1 2 D 17E9> 14E9> 11F9> CGC_DOUT<11..0>\I TL_CLK<95..0>\I CTCLK<1..0>\I RL_CLK<5..0>\I 10E4<13E4<16E4< 6F2< 8F2< 10E9< 13E9< 16E9< 2 3 4 5 6 7 14 12 10 8 6 4 25 23 22 21 20 19 18 17 16 15 5 3 9 7 IO4<6> IO4<5> IO4<4> IO4<3> IO4<2> IO4<1> IO2<10> IO2<9> IO2<8> IO2<7> IO2<6> IO2<5> IO2<4> IO2<3> IO2<2> IO2<1> IO/GTS<4> IO/GTS<3> IO/GTS<2> IO/GTS<1> C ADAP_STRB<2..0>\I SRTS_STRB<2..0>\I 17E9> 14E9> 11E9> 17E9> 14E9> 11E9> 8 9 10 11 2 1 0 2 1 0 2 1 0 CECLK<2..0>\I CICLK<2..0>\I CGC_VALID<2..0>\I CGC_SER_D<2..0>\I 4F3< 6F2< 8F2< 4G3< 6F2< 8F2< 11E9< 14D9< 17E9< 11E9< 14D9< 17E9< C 11D5> 17E9< 14D9< 11E9< AAL_SYSCLK\I NCLK<2..0>\I 56 R127 LCLK_CPLD\I RSTB\I 2 4 6 8 1 3 5 7 J7 3.3 V 24D4> 3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 21E6<> 22B8<> 26C5> 28B3<> 6C9< 8D9< B IOBLOCK 1 2 3 4 8 7 6 5 B DRAWING: CPLD_2 BLOCK CPL2 Thu Nov 22 15:05:07 2001 RN125 4.7K PMC-Sierra, Inc. A DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN CPLD_2 BLOCK ENGINEER: 10 9 8 7 6 5 4 3 BW 2 ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:27 1 OF 29 A 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H PCI_3_3V\I PCI_VCC\I 26F2< P_AD<31..0> 95 31 96 30 97 29 98 28 100 27 101 26 102 25 103 24 104 23 105 22 106 21 107 20 110 19 111 18 112 17 113 16 114 15 117 14 118 13 119 12 120 11 121 10 122 9 123 8 124 7 125 6 126 5 127 4 128 3 129 2 130 1 131 0 L_AD<31..0>\I 3.3 V 3.3 V VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 DP<3> DP<2> DP<1> DP<0> 162 147 141 133 116 109 99 89 70 62 45 35 28 20 1 139 138 137 136 134 163 144 143 148 90 149 135 146 145 91 92 153 151 150 160 142 53 154 152 159 158 157 156 155 176 161 140 132 115 108 88 69 61 44 27 19 3B10<> 4D9<> 6D9<> 8D9<> 11F5<> 14F5<> 17F5<> 21D10<> 22C4<> 28C3<> 1 0 4.7K 4 3 2 4.7K R115 7 6 5 12 11 10 A22 B22 C22 D22 E22 A20 B20 C20 D20 E20 A18 B18 C18 D18 E18 A16 B16 C16 D16 E16 18 17 16 A11 B11 C11 D11 E11 A9 B9 C9 D9 E9 A7 B7 C7 D7 E7 A5 B5 C5 D5 E5 A3 B3 C3 D3 E3 A1 B1 C1 D1 E1 F15 F17 F19 F21 F23 F25 A22 B22 C22 D22 E22 A20 B20 C20 D20 E20 A18 B18 C18 D18 E18 A16 B16 C16 D16 E16 A23 B23 C23 D23 E23 A21 B21 C21 D21 E21 A19 B19 C19 D19 E19 A17 B17 C17 D17 E17 A23 B23 C23 D23 E23 A21 B21 C21 D21 E21 9 8 0 F P_CBE<3..0> P_SERRB RN20 RN20 RN20 RN22 RN22 RN22 RN22 RN24 RN24 RN24 RN24 RN25 RN25 RN25 RN25 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 1 RN188 A24 B24 C24 D24 E24 A24 B24 C24 D24 E24 A25 B25 C25 D25 E25 A25 B25 C25 D25 E25 2 RN187 P_ENUMB 4.7K A19 B19 15 C19 14 D19 E19 13 1 P_PAR A17 B17 C17 D17 E17 A15 B15 C15 D15 E15 2 3 A10 21 B10 C10 D10 20 E10 19 A8 B8 C8 D8 E8 A6 B6 C6 D6 E6 A4 B4 C4 D4 E4 26 25 24 RN18 RN18 3 4 6 5 4.7K 4.7K 3.3 V -------- E ----A11 B11 C11 D11 E11 A9 B9 C9 D9 E9 A7 B7 C7 D7 E7 A5 B5 C5 D5 E5 A3 B3 C3 D3 E3 A1 B1 C1 D1 E1 F15 F17 F19 F21 F23 F25 P_PERRB P_STOPB P_DEVSELB P_FRAMEB P_IRDYB P_TRDYB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 2 1 0 RN111 1 2 3 4 1 RN110 2 3 4 1 RN109 2 3 4 1 RN108 2 3 4 1 RN107 2 3 4 1 RN106 2 3 4 1 RN105 2 3 4 1 RN104 2 3 4 10 8 173 7 174 6 175 2 5 8 10 3 4 7 5 6 8 5 8 10 9 7 10 6 11 5 12 8 1013 7 14 6 15 5 31 8 1032 7 33 6 34 5 36 8 1037 7 38 6 39 5 40 8 1042 7 43 6 46 5 47 8 1048 7 49 6 50 5 51 AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> LAD<31> LAD<30> LAD<29> LAD<28> LAD<27> LAD<26> LAD<25> LAD<24> LAD<23> LAD<22> LAD<21> LAD<20> LAD<19> LAD<18> LAD<17> LAD<16> LAD<15> LAD<14> LAD<13> LAD<12> LAD<11> LAD<10> LAD<9> LAD<8> LAD<7> LAD<6> LAD<5> LAD<4> LAD<3> LAD<2> LAD<1> LAD<0> G J3 G F L_BTERMB\I 28B9> PART#PCI9054-AB50PI U40 BTERM* BIGEND* LHOLDA LHOLD BLAST* LW/R* BREQO READY* LSERR* ADS* L_BLASTB L_LW/RB L_READYB L_LSERRB L_ADSB 8 7 6 5 4 PCI9054 J-MODE RN103 1 2 3 4 10 8 23 22 30 29 28 27 A15 B15 C15 D15 E15 ----A10 B10 C10 D10 E10 A8 B8 C8 D8 E8 A6 B6 C6 D6 E6 A4 B4 C4 D4 E4 A2 B2 C2 D2 E2 6 7 16 6 30 5 41 167 52 29 22 23 26 25 24 17 21 18 7 172 169 171 170 168 C/BE<3>* C/BE<2>* C/BE<1>* C/BE<0>* PME* ENUM* PAR DEVSEL* STOP* SERR* PERR* LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* GNT* PCLK INTA* RN102 1 2 3 4 2 3 4 2 3 4 10 8 7 6 5 7 6 5 7 6 5 RN101 10 1 8 P_LOCKB P_IDSEL LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* MODE<1> MODE<0> TEST VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 L_WAITB LCLK\I 4.7K 4.7K 4.7K 7 6 5 3 E 24D4> 28B9> L_INTB\I 2 RN26 3 RN26 4 RN26 3.3 V P_REQB P_CLK 31 RN99 1 2 3 4 10 8 7 6 5 LBE0* LBE1* LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LA<28> ALE DEN* DT/R* EEDI/O EESK EECS RN21 RN21 RN21 RN21 RN23 RN23 D 1 2 3 4 1 2 8 7 6 5 8 7 330 330 330 330 330 330 RN100 10 1 8 D RN26 8 4.7K 1 P_GNTB P_INTAB J5 JP6 HEADER3 166 165 164 P_RSTB A2 B2 1 C2 2 D2 3 E2 4 F1 F3 F5 F7 F9 F11 F13 8 7 6 5 1 2 3 10 R112 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 94 93 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 68 67 66 65 64 63 60 59 58 57 56 55 54 3.3 V U17 U62 NM93CS46 1 2 3 4 0 1 L_DT_RB L_DENB L_ALE 2 1 0 UP_CONTROL<8..0>\I 28B9< C F1 F3 F5 F7 F9 F11 F13 ZPACK5X22A CPCI 4.7K RN112 CS SK DI DO VCC PRE PE GND 8 7 6 5 1024-BIT SERIAL EEPROM RN19 8 4.7K7 4.7K6 4.7K5 4.7K RN20 8 4.7K LA<28..2>\I 28C9< LBE<1..0>\I 28B9< 1 2 3 4 1 3.3 V C B B VCC 3.3 V C407 0.01UF C406 0.01UF C405 0.01UF 0.1UF C409 0.1UF C408 0.1UF C410 0.1UF C412 10UF C411 10UF C404 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:28 2 1 OF 29 A A PLACE THE DECOUPLING CAPS NEAR THE CHIP. DRAWING: PCI_BLOCK PCI_BLOCK TITLE: AAL1GATOR-32 REF DESIGN CPCI & PCI9054 BW Thu Nov 22 15:05:13 2001 ENGINEER: 10 9 8 7 6 5 4 3 10 9 8 7 6 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H 3.3 V F2 7.000A G G PCI_3_3V\I 25G10> U41 LT1580CQ 2.5 V VCC VCONT SENSE 4 1 3 6 1 110 0.33UF R121 C431 100UF C430 270 R119 C429 270 C428 VCC 5 VPOWER F1 2.000A +2.5V DC SUPER_GREEN D4 R120 2 68UF 68UF 1 VOUT ADJ TAB 22UF 2 C433 220UF PCI_VCC\I 25G8> C432 110 R122 +5.0V DC SUPER_GREEN D2 1 2 2 D1 6.2V_1W F F 3.3 V E 1 2 +3.3V DC SUPER_GREEN D3 R123 E D 270 D 3.3 V SW1 2 PBNO 1 1 2 U42 MR SENSE HYST GND VCC CTL RESET RESET 8 7 6 5 C 3.3 V 931 R126 10K R124 3 4 C RSTB\I 3C10<> 4D9<> 11E5<> 14E5<> 17E6<> 21E6<> 22B8<> 28B3<> 29B5<> 6C9< 8D9< MAX700 1.0K R125 RESET CIRCUITRY B B PMC-Sierra, Inc. A DRAWING: POWER_AND_RESET POWER_BLOCK Thu Nov 22 15:06:03 2001 ENGINEER: 10 9 8 7 6 5 4 3 BW 2 DOCUMENT NUMBER: PMC-1990887 DOCUMENT ISSUE NUMBER: TITLE: AAL1GATOR-32 REF DESIGN POWER AND RESET BLOCK ISSUE DATE: JAN 2001 REVISION NUMBER: 3.0 PAGE:29 1 OF 29 A RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 11 APPENDIX B: U47 MICROPROCESSOR CPLD VHDL CODE -- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 2000 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer program may -- be used, modified, reproduced, or distributed in any form by any means -- without the prior written permission of PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, confidential -- business information and commercial or financial information (collectively, -- the "information") of PMC-Sierra, Inc., or unlawful disclosure of any or all -- of the information may cause irreparable harm and result in significant -- commercial and competitive loss to PMC-Sierra, Inc. -- ----------------------------------------------------------------------- ----------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- ----------------------------------------------------------------------- Project :PMC-990887 -- File Name :adetect.vhd -- Path : -- Designer :KM --- Revision History -- Issue Date Initial Descriptions -- 1 10/12/99 KM --- Function -- This is a VHDL code for the AAL1gator-32 Reference Design. -- This code generates ADETECT signals for AAL1gator-32 devices. -- ---------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; entity ADETECTgenerator is port ( -- input AACTIVE signals to the CPLD: AACTIVE : in std_logic_vector (3 downto 1); -- output ADETECT signals from the CPLD: ADETECT : out std_logic_vector (3 downto 1) ); end ADETECTgenerator; architecture ADETECTgenerator_arch of ADETECTgenerator is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN begin -process(AACTIVE) -begin ADETECT(1) <= AACTIVE(2) or AACTIVE(3); ADETECT(2) <= AACTIVE(1) or AACTIVE(3); ADETECT(3) <= AACTIVE(1) or AACTIVE(2); -end process; end ADETECTgenerator_arch; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 2000 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer program may -- be used, modified, reproduced, or distributed in any form by any means -- without the prior written permission of PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, confidential -- business information and commercial or financial information (collectively, -- the "information") of PMC-Sierra, Inc., or unlawful disclosure of any or all -- of the information may cause irreparable harm and result in significant -- commercial and competitive loss to PMC-Sierra, Inc. -- ----------------------------------------------------------------------- ----------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- ----------------------------------------------------------------------- Project :PMC-990887 -- File Name :chipaddress.vhd -- Path : -- Designer :KM --- Revision History -- Issue Date Initial Descriptions -- 1 10/13/99 KM Preliminary --- Function -- This is a VHDL code for the ASAP-CES Reference Design. -- This code generates the CHIP_ADDRESS<19..0> signals to SPECTRA-155, -- TEMUX , APEX, ATLAS and AAL1gator-32 devices. -- ---------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity CHIPADgeneration is port ( -- input signals to the CPLD L_ADSB : in std_logic; L_ALE : in std_logic; L_DENB : in std_logic; L_DT_RB : in std_logic; L_READYB : in std_logic; L_BLASTB : in std_logic; L_LW_RB : in std_logic; L_AD : inout std_logic_vector(31 downto 0); -- reset signal PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN RSTB : inout std_logic; -- CPLD clock: LCLK_CPLD : in std_logic; -- output signals: CHIP_ADDRESS : out std_logic_vector(19 downto 0) := (others => 'Z') ); end CHIPADgeneration; architecture CHIPADgeneration of CHIPADgeneration is signal RDB : std_logic; signal WRB : std_logic; begin process(LCLK_CPLD, L_ADSB, L_ALE, L_DT_RB, L_DENB) begin if (LCLK_CPLD'event and LCLK_CPLD = '1') then if (L_ADSB = '0' and L_ALE = '1' and L_BLASTB = '1' and L_DENB = '1') then CHIP_ADDRESS(19 downto 0) <= L_AD(19 downto 0); -starting a single read cycle: if (L_LW_RB = '0' and L_DT_RB = '0' and L_READYB = '1') then RDB <= '0'; -starting a single write cycle: elsif (L_LW_RB = '1' and L_DT_RB = '1' and L_READYB = '1') then WRB <= '0'; end if; else CHIP_ADDRESS(19 downto 0) <= (others => 'X'); end if; end if; end process; end CHIPADgeneration; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 2000 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer program may -- be used, modified, reproduced, or distributed in any form by any means -- without the prior written permission of PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, confidential -- business information and commercial or financial information (collectively, -- the "information") of PMC-Sierra, Inc., or unlawful disclosure of any or all -- of the information may cause irreparable harm and result in significant -- commercial and competitive loss to PMC-Sierra, Inc. -- ----------------------------------------------------------------------- ----------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- ----------------------------------------------------------------------- Project :PMC-990887 -- File Name :chipselect.vhd -- Path : -- Designer :KM --- Revision History -- Issue Date Initial Descriptions -- 1 10/12/99 KM Preliminary --- Function -- This is a VHDL code for the ASAP-CES Reference Design. -- This code generates chip select signals for SPECTRA-155, TEMUX, -- APEX, ATLAS and AAL1gator-32 devices. -- ---------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity CSBgeneration is port ( -- input address lines to the CPLD LA : in std_logic_vector (28 downto -- reset signal RSTB : inout std_logic; -- Chip select signals: APEX_CSB : out std_logic; -- chip ATLAS_CSB : out std_logic; -- chip AAL1_CSB : out std_logic; -- chip AAL2_CSB : out std_logic; -- chip AAL3_CSB : out std_logic; -- chip 20); select select select select select to to to to to APEX ATLAS AAL1gator 1 AAL1gator 2 AAL1gator 3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN TE1_CSB : out std_logic; -- chip select to TEMUX 1 TE2_CSB : out std_logic; -- chip select to TEMUX 2 TE3_CSB : out std_logic; -- chip select to TEMUX 3 SPECTRA_CSB : out std_logic -- chip select to SPECTRA-155 ); end CSBgeneration; architecture CSBgeneration of CSBgeneration is begin process(LA, RSTB) begin if RSTB = '0' then APEX_CSB <= '1'; ATLAS_CSB <= '1'; AAL1_CSB <= '1'; AAL2_CSB <= '1'; AAL3_CSB <= '1'; TE1_CSB <= '1'; TE2_CSB <= '1'; TE3_CSB <= '1'; SPECTRA_CSB <= '1'; else case LA is when "000000001" => APEX_CSB <= '0'; when "000000010" => ATLAS_CSB <= '0'; when "000000100" => AAL1_CSB <= '0'; when "000001000" => AAL2_CSB <= '0'; when "000010000" => AAL3_CSB <= '0'; when "000100000" => TE1_CSB <= '0'; when "001000000" => TE2_CSB <= '0'; when "010000000" => TE3_CSB <= '0'; when "100000000" => SPECTRA_CSB <= '0'; when OTHERS => SPECTRA_CSB <= '1'; -- do nothing end case; end if; end process; end CSBgeneration; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 2000 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer program may -- be used, modified, reproduced, or distributed in any form by any means -- without the prior written permission of PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, confidential -- business information and commercial or financial information (collectively, -- the "information") of PMC-Sierra, Inc., or unlawful disclosure of any or all -- of the information may cause irreparable harm and result in significant -- commercial and competitive loss to PMC-Sierra, Inc. -- ----------------------------------------------------------------------- ----------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- ----------------------------------------------------------------------- Project :PMC-990887 -- File Name :clocking.vhd -- Path : -- Designer :KM --- Revision History -- Issue Date Initial Descriptions -- 1 08/27/99 KM Preliminary --- Function -- This is a VHDL code for the ASAP-CES Reference Design. -- This code generates clock signals for SPECTRA-155, TEMUXes,and AAL1gator32s -- ---------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity CLKgeneration is port ( -- input clocks to the CPLD: 51.84 MHz, 37.056 MHz, and 19.44 MHz clk52 : in std_logic; clk37 : in std_logic; clk19 : in std_logic; -- CPLD outputs: CLK_RRCLK : out std_logic; -- to SPECTRA-155 CLK_TRCLK : out std_logic; -- to SPECTRA-155 CLK_DCK : out std_logic; -- to SPECTRA-155 CLK_ACK : out std_logic; -- to SPECTRA-155 CLK_LREFCLK : out std_logic; -- to TEMUXes PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN CLK_SREFCLK : out std_logic; -- to TEMUXes and AAL1gator-32s CLK_CLK52M : out std_logic; -- to TEMUXes CLK_FASTCLK : out std_logic; -- to AAL1gator-32s CLK_XCLK : out std_logic -- to TEMUXes ); end CLKgeneration; architecture CLKgeneration of CLKgeneration is begin CLK_RRCLK <= clk19; CLK_TRCLK <= clk19; CLK_DCK <= clk19; CLK_ACK <= clk19; CLK_LREFCLK <= clk19; CLK_SREFCLK <= clk19; CLK_CLK52M <= clk52; CLK_FASTCLK <= clk52; CLK_XCLK <= clk37; end CLKgeneration; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 33 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 2000 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer program may -- be used, modified, reproduced, or distributed in any form by any means -- without the prior written permission of PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, confidential -- business information and commercial or financial information (collectively, -- the "information") of PMC-Sierra, Inc., or unlawful disclosure of any or all -- of the information may cause irreparable harm and result in significant -- commercial and competitive loss to PMC-Sierra, Inc. -- ----------------------------------------------------------------------- ----------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- ----------------------------------------------------------------------- Project :PMC-990887 -- File Name :framepulse.vhd -- Path : -- Designer :KM --- Revision History -- Issue Date Initial Descriptions -- 1 08/27/99 KM Preliminary --- Function -- This is a VHDL code for the ASAP-CES Reference Design. -- This code generates frame pulses for SPECTRA-155, TEMUX, -- and AAL1gator-32 devices for the Telecombus and SBI interfaces. -- The generated frame pulses are 2 kHz. -- ---------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity FPgenerator is port ( clk19 : in std_logic; -- input clock to the CPLD: 19.44 MHz RESET : in std_logic; count : out std_logic_vector (13 downto 0); -- CPLD outputs frame_DFP : out std_logic; -- frame pulse to SPECTRA-155 frame_C1FP : out std_logic; -- frame pulse to TEMUXes and AAL1gator-32s PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN frame_LAC1 : out std_logic ); end FPgenerator; -- frame pulse to TEMUXes architecture FPgenerator_arch of FPgenerator is begin process(clk19) variable count_int : std_logic_vector (13 downto 0); begin -- 2 kHz frame pulses are sampled at rising edge of the 19.44 MHz clock and -- happens every 9720 pulses. if clk19 = '1' and clk19'event then if RESET = '1' then count_int := "00000000000000"; frame_C1FP <= '0'; frame_LAC1 <= '0'; frame_DFP <= '0'; else if count_int = 9719 then frame_C1FP <= '1'; frame_LAC1 <= '1'; frame_DFP <= '1'; count_int := (others => '0'); count <= count_int; else count_int := count_int + 1; frame_C1FP <= '0'; frame_LAC1 <= '0'; frame_DFP <= '0'; count <= count_int; end if; end if; end if; end process; end FPgenerator_arch; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 2000 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer program may -- be used, modified, reproduced, or distributed in any form by any means -- without the prior written permission of PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, confidential -- business information and commercial or financial information (collectively, -- the "information") of PMC-Sierra, Inc., or unlawful disclosure of any or all -- of the information may cause irreparable harm and result in significant -- commercial and competitive loss to PMC-Sierra, Inc. -- ----------------------------------------------------------------------- ----------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- ----------------------------------------------------------------------- Project :PMC-990887 -- File Name :interrupt.vhd -- Path : -- Designer :KM --- Revision History -- Issue Date Initial Descriptions -- 1 10/13/99 KM Preliminary --- Function -- This is a VHDL code for the ASAP-CES Reference Design. -- This code generates the L_INTB signal from the INTB signals of SPECTRA-155, -- TEMUX , APEX, ATLAS and AAL1gator-32 devices. -- ---------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity INTBgeneration is port ( -- input interrput signals to the CPLD SPECTRA_INTB : in std_logic; TE1_INTB : in std_logic; TE2_INTB : in std_logic; TE3_INTB : in std_logic; AAL1_INTB : in std_logic; AAL2_INTB : in std_logic; AAL3_INTB : in std_logic; APEX_INTLOB : in std_logic; APEX_INTHIB : in std_logic; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN ATLAS_INTB : in std_logic; reset signal RSTB : inout std_logic; -- output signal: L_INTB : out std_logic ); end INTBgeneration; architecture INTBgeneration of INTBgeneration is begin process(RSTB, SPECTRA_INTB, TE1_INTB, TE2_INTB, TE3_INTB, AAL1_INTB, AAL2_INTB, AAL3_INTB, APEX_INTLOB, APEX_INTHIB, ATLAS_INTB) begin if RSTB = '0' then L_INTB <= '1'; else L_INTB <= (SPECTRA_INTB and TE1_INTB and TE2_INTB and TE3_INTB and AAL1_INTB and AAL2_INTB and AAL3_INTB and APEX_INTLOB and APEX_INTHIB and ATLAS_INTB); end if; end process; end INTBgeneration; -- PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -- PMC-Sierra, Inc. -- PROPRIETARY AND CONFIDENTIAL --- Copyright 2000 PMC-Sierra, Inc. --- All rights reserved. No part of this documentation or computer program may -- be used, modified, reproduced, or distributed in any form by any means -- without the prior written permission of PMC-Sierra, Inc. --- This documentation and computer program contains trade secrets, confidential -- business information and commercial or financial information (collectively, -- the "information") of PMC-Sierra, Inc., or unlawful disclosure of any or all -- of the information may cause irreparable harm and result in significant -- commercial and competitive loss to PMC-Sierra, Inc. -- ----------------------------------------------------------------------- ----------------------------------------------------------------------- PMC-Sierra, Inc. -- 105 - 8555 Baxter Place -- Burnaby, B.C. -- Canada V5A 4V7 -- Tel: 604-415-6000 -- Fax: 604-415-6206 -- email: apps@pmc-sierra.com -- ----------------------------------------------------------------------- Project :PMC-990887 -- File Name :networkclock.vhd -- Path : -- Designer :KM --- Revision History -- Issue Date Initial Descriptions -- 1 10/08/99 KM --------Function: This is a VHDL code for the AAL1gator-32 Reference Design. This code generates NCLK clock signal for the AAL1gator-32 devices from AAL_SYSCLK (38.88 MHz). This code divides the AAL_SYSCLK by 16 to generate the NCLK clock. The generated clock is 2.43 MHz. ---------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity NetClkgeneration is port ( -- CPLD inputs: -- input clock to the CPLD: 38.88 MHz aal_sysclk : in std_logic; -- input reset signal RSTB : in std_logic; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -- CPLD outputs: nclk : out std_logic -- to AAL1gator-32s ); end NetClkgeneration; architecture NetClkgeneration of NetClkgeneration is constant max_count: integer := 8; signal divided_clk : std_logic := '0'; begin process(aal_sysclk, RSTB) variable count: integer:= 0; begin if (RSTB = '0') then divided_clk <= '0'; count := 0; elsif (aal_sysclk'event and aal_sysclk = '1') then count := count + 1; if (count = max_count) then divided_clk <= not divided_clk; count := 0; end if; end if; end process; nclk <= divided_clk; end NetClkgeneration; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 12 APPENDIX C: EXTERNAL DS3 SRTS VHDL CODE --Copyright (C) 1995-1998. PMC-Sierra, Inc. All Rights Reserved. ---- DESIGN TITLE: AAL1GATOR32 DS3 SRTS -- FILE NAME: a32-v1.vhd --- DETAILED REVISION HISTORY --- ISSUE DATE(YY/MM/DD) NAME DESCRIPTION -- 00 00/06/12 creation --------------------------------------------------------------------------------- FUNCTION: AAL1GATOR-32 External Implementation for DS3 SRTS -Features Include: -- Interaface to the A-32 SRTS strobe and data signals -- Mapping the 4 bits SRTS code to 8 bits D/A converter data -- Generates DAC write pulse ----------------------------------------------------------------------------------Synthesis Options: -FSM Synthesis: Binary -FSM synthesis: Interpretation of VHDL 'when others' : Fasterst & smallest -Export schematics to Vhdl -Input XNF Bus Style: %s<%d> -Default Frequency: 16 --- Synthesis/implementation -Top Level: AAL1GATOR -Family XC4000XLA -Device XC4044XLA-09HQ304C -Speed Grade -09 -Target Clock Frequency: 16 -optimize for: Speed -Effort: High -Insert I/O pads --- Implementation Options -User Constraints: c:\ PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -Implemntation: Optimize Speed -Simulation: Generic Vhdl -Produce Configuration Data --- XC4000 Implemation Options: -- Basic: -- Y Use Global Clocks -- Y Use Global Output enables -- Y Use Global Set/Reset -- Y Use Timing constraints -- Y Use Design Location Constraints --Macrocell Power setting: Std -Output Slew Rate: Fast -- Advanced: -- N Use Timing Optimization -- Y Use Multi-level Logic Optimization -- Y Use Advanced fitting -- Y Enable D <--> T Type Transform Optimization --Collapsing Pterm Limit: 20 -Collapsing Input Limit (XC9500XL only): 36 --- Programming: -Signature / User Code: use design name ------------------------------------------------------------------------------- design files --- a32-v1.vhd: top level (this file) -- a32-v1.ucf: user contraint file (timing and pin out) -- tbd.vhd: test bench ---- LIBRARIES -lIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_arith.all; USE IEEE.STD_LOGIC_unsigned.all; -- pragma translate_off LIBRARY unisim; USE unisim.Vcomponents.all; -- pragma translate_on PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN --EJECT_ -------------------------------------------------------------------------------- Entity : ds3srts --- Author(s) : -- Organization : PMC-Sierra --- Project : AAL1GATOR-32 DS3 SRTS FPGA --- Creation Date : 000612 --- Description : ------------------------------------------------------------------------------ENTITY ds3srts IS PORT ( sys_clk: IN brd_rstb: rstb: rstb_out: STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; OUT STD_LOGIC; cgc_dout: cgc_line: srts_stbh: dac_csb: OUT dac_wrb: OUT dac_abb: OUT dac_dout: -- test stuff test_in: test_rstb: test_cgcstbh: test_cgcdout: test_cgcline: IN IN IN STD_LOGIC_VECTOR(3 downto 0); STD_LOGIC_VECTOR(4 downto 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; OUT STD_LOGIC_VECTOR(7 downto 0); IN OUT OUT OUT OUT STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(3 downto 0); STD_LOGIC_VECTOR(4 downto 0); PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN test_csb: OUT test_wrb: OUT test_abb: OUT -- changed to input test_dout: OUT ); END ds3srts; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(7 downto 0) ARCHITECTURE rtl OF ds3srts IS --This device is used on the DS3 SRTS FTP. --It is derived from the AAL1GATOR-2 DS3 board design. --It implements the a/d bus controls, as well as translating --the 4 bit serial SRTS code to an 8 bit code for the D/A. -- 6/12/00 Initial construction -type statetype is (IDLE, S1, S2, S3, S4, S5); --- CONSTANTS/SIGNAL DECLARATIONS --- registered input SIGNAL cgc_dout_reg : STD_LOGIC_VECTOR(3 SIGNAL cgc_line_reg : STD_LOGIC_VECTOR(4 SIGNAL cgc_dout_reg2 : STD_LOGIC_VECTOR(3 SIGNAL cgc_line_reg2 : STD_LOGIC_VECTOR(4 SIGNAL srts_stbh_reg : STD_LOGIC; SIGNAL dac_d SIGNAL nextstate SIGNAL test_dout_reg SIGNAL clk SIGNAL rst : : : : downto downto downto downto 0); 0); 0); 0); -- STD_LOGIC_VECTOR(7 downto 0); statetype; STD_LOGIC_VECTOR(7 downto 0); STD_LOGIC; : STD_LOGIC; COMPONENT BUFG PORT (i: IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; --component STARTUP -port (GSR: in std_logic); -- end component; component INV PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN port (I: in STD_LOGIC; O: out STD_LOGIC); end component; BEGIN rstb_out <= rstb; -dac_dout <= test_dout; --clk_buf: BUFG -- PORT MAP(i => sys_clk, o => clk); --U1: STARTUP port map (GSR=>rst); --U2: INV port map(I => brd_rstb, O => rst); inp_data_latch: PROCESS(sys_clk, brd_rstb, cgc_dout, cgc_line, srts_stbh) BEGIN IF (brd_rstb = '0') THEN cgc_dout_reg <= "0000"; cgc_line_reg <= "00000"; cgc_dout_reg2 <= "0000"; cgc_line_reg2 <= "00000"; srts_stbh_reg <= '0'; test_rstb <= '0'; test_cgcstbh <= '1'; test_cgcline <= "00000"; test_cgcdout <= "0000"; test_dout_reg <= "10000001"; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN test_rstb <= brd_rstb; test_cgcstbh <= srts_stbh; -- changed to get a more stable cgc_line test output test_cgcline <= cgc_line_reg; test_cgcdout <= cgc_dout; -- test_dout_reg <= test_dout; -- test_cgcline <= "00000"; srts_stbh_reg <= srts_stbh; cgc_dout_reg <= cgc_dout; cgc_line_reg <= cgc_line; cgc_line_reg <= "00000"; IF srts_stbh_reg = '1' THEN cgc_dout_reg2 <= cgc_dout_reg; cgc_line_reg2 <= cgc_line_reg; -- PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN END IF; END IF; END PROCESS inp_data_latch; statemc: PROCESS(sys_clk, brd_rstb, nextstate, srts_stbh_reg, cgc_line_reg2) BEGIN IF (brd_rstb = '0') THEN nextstate <= IDLE; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN CASE nextstate IS WHEN IDLE => IF srts_stbh_reg = '0' THEN nextstate <= IDLE; ELSE nextstate <= S1; END IF; WHEN S1 => nextstate <= S2; WHEN S2 => -- changed to uncondition S3, 'cause I don't know the line number -IF cgc_line_reg2 = "00000" OR cgc_line_reg2 = "00010" THEN nextstate <= S3; -ELSE -nextstate <= IDLE; -END IF; WHEN S3 => nextstate <= S4; WHEN S4 => nextstate <= S5; WHEN S5 => nextstate <= IDLE; WHEN OTHERS => nextstate <= IDLE; END CASE; END IF; END PROCESS statemc; convert_proc: PROCESS(sys_clk, brd_rstb, cgc_dout_reg2) BEGIN IF (brd_rstb = '0') THEN dac_d <= "00000000"; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN CASE cgc_dout_reg2 IS -WHEN "0000" => dac_d <= "10000010"; -- 80 -WHEN "0001" => dac_d <= "10001101"; -- 8D PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN ---------------- WHEN "0010" => dac_d <= "10011010"; WHEN "0011" => dac_d <= "10100110"; WHEN "0100" => dac_d <= "10110011"; WHEN "0101" => dac_d <= "11000000"; WHEN "0110" => dac_d <= "11001101"; WHEN "0111" => dac_d <= "11100111"; WHEN "1000" => dac_d <= "00011001"; WHEN "1001" => dac_d <= "00100110"; WHEN "1010" => dac_d <= "00110011"; WHEN "1011" => dac_d <= "01000000"; WHEN "1100" => dac_d <= "01001101"; WHEN "1101" => dac_d <= "01011010"; WHEN "1110" => dac_d <= "01100110"; WHEN "1111" => dac_d <= "01110011"; WHEN others => dac_d <= "10000100"; WHEN "1000" => dac_d <= "00011010"; WHEN "1001" => dac_d <= "00100111"; WHEN "1010" => dac_d <= "00110100"; WHEN "1011" => dac_d <= "01000000"; WHEN "1100" => dac_d <= "01001101"; WHEN "1101" => dac_d <= "01011010"; WHEN "1110" => dac_d <= "01100110"; WHEN "1111" => dac_d <= "01110011"; WHEN "0000" => dac_d <= "10000000"; WHEN "0001" => dac_d <= "10001001"; WHEN "0010" => dac_d <= "10010011"; WHEN "0011" => dac_d <= "10011100"; WHEN "0100" => dac_d <= "10100110"; WHEN "0101" => dac_d <= "10101111"; WHEN "0110" => dac_d <= "10111001"; WHEN "0111" => dac_d <= "11000010"; WHEN others => dac_d <= "10000000"; END CASE; END IF; END PROCESS convert_proc; -- 9A -- A6 -- B3 -- C0 -- CD -- E7 -- 19 -- 26 -- 33 -- 40 -- 4D -- 5A -- 66 -- 73 -- 80 -- 19 -> -- 26 -> -- 33 -> -- 40 -> -- 4D -> -- 5A -> -- 66 -> -- 73 -> -- 80 -> -- 8D -> -- 9A -> -- A6 -> -- B3 -> -- C0 -> -- CD -> -- E7 -> -- 80 1A 27 34 40 4D 5A 66 73 80 89 93 9C A6 AF B9 C2 oup_data_latch: PROCESS(sys_clk, brd_rstb, dac_d, test_in, test_dout_reg) BEGIN IF (brd_rstb = '0') THEN test_dout <= "10000000"; dac_dout <= "10000000"; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN test_dout <= dac_d; dac_dout <= dac_d; -IF (test_in = '1') THEN -dac_dout <= test_dout_reg; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN ---- ELSE dac_dout <= dac_d; END IF; END IF; END PROCESS oup_data_latch; oup_ctl: PROCESS(sys_clk, brd_rstb, dac_d, cgc_line_reg2, nextstate) BEGIN IF (brd_rstb = '0') THEN dac_csb <= '1'; dac_wrb <= '1'; dac_abb <= '0'; test_csb <= '1'; test_wrb <= '1'; test_abb <= '0'; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN IF (nextstate = S3 or nextstate = S5) THEN dac_csb <= '0'; test_csb <= '0'; dac_wrb <= '1'; test_wrb <= '1'; ELSIF nextstate = S4 and cgc_line_reg2 = "00000" THEN dac_csb <= '0'; dac_wrb <= '0'; test_csb <= '0'; test_wrb <= '0'; dac_abb <= '0'; test_abb <= '0'; ELSIF nextstate = S4 and cgc_line_reg2 /= "00000" THEN dac_csb <= '0'; dac_wrb <= '0'; test_csb <= '0'; test_wrb <= '0'; dac_abb <= '0'; test_abb <= '0'; dac_abb <= '1'; test_abb <= '1'; ELSE dac_csb <= '1'; dac_wrb <= '1'; dac_abb <= '0'; test_csb <= '1'; test_wrb <= '1'; test_abb <= '0'; END IF; END IF; END PROCESS oup_ctl; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 47 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN END; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 48 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN 13 APPENDIX D: EXTERNAL DS3 ADAPTIVE CLOCK RECOVERY VHDL CODE ------------------------------------------------------------------------------Copyright (C) 1995-1998. PMC-Sierra, Inc. All Rights Reserved. --- DESIGN TITLE: AAL1GATOR-32 DS3 Adaptive Clock Recovery --- REVISION HISTORY -- ISSUE DATE(YY/MM/DD) DESCRIPTION -- 00 2000/06/12 creation -- 01 2001/10/02 changed nominal DS3 buffer depth from -00000001000000 (64 bytes/R_CDVT=2/11 us) -to 01010111000000 (5568 bytes/R_CDVT=174/996 us) -because 11 us is too small, and 996 us seems -more realistic. ------------------------------------------------------------------------------- FUNCTION: AAL1GATOR-32 External FPGA Implementation for DS3 Adaptive Clock -Recovery. -Features: -- Interfaces to the AAL1gator-32 CGC port. -- Captures DS3 Buffer Underrun status and buffer depth for -two DS3 signals. -- Converts DS3 Buffer Underrun status and depth to an 8-bit -DAC code (Analog Devices AD7302 Dual Voltage Output 8-bit -DAC). -- Generates DAC write access to either DAC A or DAC B of the -AD7302. --- SUMMARY OF PROCESSES: -inp_data_latch: latch CGC port outputs CGC_DOUT, CGC_LINE, and ADAP_STBH. -statemc: state machine follows CGC Channel Status(S1-S4) and CGC Buffer -Depth (D1-D6) playout states, and generates states (R1-R4) to -enable generation of DAC write accesses. -line_dout: captures DS3 line number (line_code) and DS3 Buffer depth -(buf_depth) from the CGC port. If the DS3 Buffer is in -underrun, then the buf_depth is set to nominal. -convert_proc: converts the raw DS3 Buffer depth to an AD7302 DAC code. -oup_data_latch: latches DAC code. -oup_ctl: generates the DAC write access control signals, based on -statemc states. ----------------------------------------------------------------------------------Synthesis Options: -FSM Synthesis: Binary PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 49 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN -FSM synthesis: Interpretation of VHDL 'when others' : Fasterst & smallest -Export schematics to Vhdl -Input XNF Bus Style: %s<%d> -Default Frequency: 16 --- Synthesis/implementation -Top Level: AAL1GATOR -Family XC4000XLA -Device XC4044XLA-09HQ304C (note: this device contained other logic in -addition to this DS3 Adaptive Clock Recovery logic.) -Speed Grade -09 -Target Clock Frequency: 16 -optimize for: Speed -Effort: High -Insert I/O pads --- Implementation Options -User Constraints: c:\ -Implemntation: Optimize Speed -Simulation: Generic Vhdl -Produce Configuration Data --- XC4000 Implementation Options: -- Basic: -- Y Use Global Clocks -- Y Use Global Output enables -- Y Use Global Set/Reset -- Y Use Timing constraints -- Y Use Design Location Constraints --Macrocell Power setting: Std -Output Slew Rate: Fast -- Advanced: -- N Use Timing Optimization -- Y Use Multi-level Logic Optimization -- Y Use Advanced fitting -- Y Enable D <--> T Type Transform Optimization --Collapsing Pterm Limit: 20 -Collapsing Input Limit (XC9500XL only): 36 --- Programming: -Signature / User Code: use design name -----------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 50 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN USE IEEE.STD_LOGIC_arith.all; USE IEEE.STD_LOGIC_unsigned.all; -- pragma translate_off LIBRARY unisim; USE unisim.Vcomponents.all; -- pragma translate_on ------------------------------------------------------------------------------- Entity : ds3adap -----------------------------------------------------------------------------ENTITY ds3adap IS PORT( sys_clk: IN STD_LOGIC; brd_rstb: IN STD_LOGIC; rstb: IN STD_LOGIC; cgc_dout: cgc_line: adap_stbh: dac_csb: OUT dac_wrb: OUT dac_abb: OUT dac_dout: rstb_out: -- test stuff test_in: test_rstb: test_cgcstbh: test_cgcdout: test_cgcline: IN IN IN STD_LOGIC_VECTOR(3 downto 0); STD_LOGIC_VECTOR(4 downto 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; OUT STD_LOGIC_VECTOR(7 downto 0); OUT IN OUT OUT OUT OUT STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(3 downto 0); STD_LOGIC_VECTOR(4 downto 0); test_csb: OUT test_wrb: OUT test_abb: OUT -- changed to input test_depth2_0 : OUT test_dout: OUT ); END ds3adap; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(2 downto 0); STD_LOGIC_VECTOR(7 downto 0) ARCHITECTURE rtl OF ds3adap IS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 51 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN type statetype is (IDLE, D1, D2, D3, D4, D5, D6, S1, S2, S3, S4, R1, R2, R3, R4); --- CONSTANTS/SIGNAL DECLARATIONS --- registered input SIGNAL cgc_dout_reg : STD_LOGIC_VECTOR(3 downto 0); SIGNAL cgc_line_reg : STD_LOGIC_VECTOR(4 downto 0); SIGNAL cgc_dout_reg2 : STD_LOGIC_VECTOR(3 downto 0); -SIGNAL cgc_line_reg2 : STD_LOGIC_VECTOR(4 downto 0); SIGNAL adap_stbh_reg : STD_LOGIC; SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL SIGNAL -dac_d nextstate test_dout_reg clk buf_depth line_code : : : : : : STD_LOGIC_VECTOR(7 downto 0); statetype; STD_LOGIC_VECTOR(7 downto 0); STD_LOGIC; STD_LOGIC_VECTOR(13 downto 0); STD_LOGIC_VECTOR(4 downto 0); : STD_LOGIC; SIGNAL rst COMPONENT BUFG PORT (i: IN STD_LOGIC; o : OUT STD_LOGIC); END COMPONENT; --component STARTUP -port (GSR: in std_logic); -- end component; component INV port (I: in STD_LOGIC; O: out STD_LOGIC); end component; BEGIN -- dac_dout <= test_dout; --clk_buf: BUFG -- PORT MAP(i => sys_clk, o => clk); --U1: STARTUP port map (GSR=>rst); PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 52 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN --U2: INV port map(I => brd_rstb, O => rst); rstb_out <= rstb; inp_data_latch: PROCESS(sys_clk, brd_rstb, cgc_dout, cgc_line, adap_stbh) BEGIN IF (brd_rstb = '0') THEN cgc_dout_reg <= "0000"; cgc_line_reg <= "00000"; cgc_dout_reg2 <= "0000"; -cgc_line_reg2 <= "00000"; adap_stbh_reg <= '0'; test_rstb <= '0'; test_cgcstbh <= '1'; test_cgcline <= "00000"; test_cgcdout <= "0000"; test_dout_reg <= "10000001"; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN test_rstb <= brd_rstb; test_cgcstbh <= adap_stbh; test_cgcline <= cgc_line; test_cgcdout <= cgc_dout; -- test_dout_reg <= test_dout; test_cgcline <= "00000"; adap_stbh_reg <= adap_stbh; cgc_dout_reg <= cgc_dout; cgc_line_reg <= cgc_line; IF adap_stbh_reg = '1' THEN cgc_dout_reg2 <= cgc_dout_reg; cgc_line_reg2 <= cgc_line_reg; END IF; END IF; END PROCESS inp_data_latch; -- statemc: PROCESS(sys_clk, brd_rstb, nextstate, adap_stbh_reg, cgc_line_reg) BEGIN IF (brd_rstb = '0') THEN nextstate <= IDLE; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN CASE nextstate IS WHEN IDLE => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "00101" THEN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 53 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN nextstate <= D1; ELSIF cgc_line_reg = "01111" nextstate <= S1; ELSE nextstate <= IDLE; END IF; WHEN D1 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "00100" nextstate <= D2; ELSE nextstate <= IDLE; END IF; WHEN D2 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "00011" nextstate <= D3; ELSE nextstate <= IDLE; END IF; WHEN D3 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "00010" nextstate <= D4; ELSE nextstate <= IDLE; END IF; WHEN D4 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "00001" nextstate <= D5; ELSE nextstate <= IDLE; END IF; WHEN D5 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "00000" nextstate <= D6; ELSE nextstate <= IDLE; END IF; WHEN D6 => THEN THEN THEN THEN THEN THEN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 54 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN nextstate <= R1; WHEN S1 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "01110" THEN nextstate <= S2; ELSE nextstate <= IDLE; END IF; WHEN S2 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "01101" THEN nextstate <= S3; ELSE nextstate <= IDLE; END IF; WHEN S3 => IF adap_stbh_reg = '0' THEN nextstate <= IDLE; ELSIF cgc_line_reg = "01100" THEN nextstate <= S4; ELSE nextstate <= IDLE; END IF; WHEN S4 => nextstate <= R1; WHEN R1 => nextstate <= WHEN R2 => nextstate <= WHEN R3 => nextstate <= WHEN R4 => nextstate <= WHEN OTHERS => nextstate <= END CASE; END IF; END PROCESS statemc; R2; R3; R4; IDLE; IDLE; line_dout : PROCESS(sys_clk, brd_rstb, cgc_dout_reg2) BEGIN IF (brd_rstb = '0') THEN buf_depth <= "00000000000000"; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 55 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN line_code <= "00000"; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN CASE nextstate IS WHEN D1 => line_code(2 downto 0) <= cgc_dout_reg2(3 downto 1); WHEN D3 => line_code(4 downto 3) <= cgc_dout_reg2(3 downto 2); buf_depth(13 downto 12) <= cgc_dout_reg2(1 downto 0); WHEN D4 => buf_depth(11 downto 8) <= cgc_dout_reg2(3 downto 0); WHEN D5 => buf_depth(7 downto 4) <= cgc_dout_reg2(3 downto 0); WHEN D6 => buf_depth(3 downto 0) <= cgc_dout_reg2(3 downto 0); WHEN S1 => line_code(2 downto 0) <= cgc_dout_reg2(2 downto 0); WHEN S3 => IF cgc_dout_reg2 /= "0000" THEN -- (original) buf_depth <= "00000001000000"; -- set nominal buffer depth, during underrun, -- to 5568 bytes, corresponding to -- R_CDVT=174=0x00AE (996 us) -- note: nominal buf_depth is chosen such that -nominal buf_depth(6:3)="1000" to simplify -logic, and tolerance to CDV is approximately -one millisecond. buf_depth <= "01010111000000"; -- 0x15C0 END IF; WHEN S4 => line_code(4 downto 3) <= cgc_dout_reg2(1 downto 0); WHEN OTHERS => NULL; END CASE; END IF; END PROCESS line_dout; convert_proc: PROCESS(sys_clk, brd_rstb, buf_depth) BEGIN IF (brd_rstb = '0') THEN dac_d <= "00000000"; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN -- (original) IF buf_depth(13 downto 7) /= "0000000" THEN -- (original) dac_d <= "11010101"; -IF buf_depth(13 downto 7) > "0101011" THEN -- buffer too full, speed up DS3 clock. dac_d <= "11010101"; -- D5 ELSIF buf_depth(13 downto 7) < "0101011" THEN -- buffer too empty, slow down DS3 clock. dac_d <= "00001101"; -- 0D ELSE -- buffer depth is in proper range of nominal. CASE buf_depth(6 downto 3) IS WHEN "1111" => dac_d <= "11001100"; -- CC WHEN "1110" => dac_d <= "11000010"; -- C2 WHEN "1101" => dac_d <= "10111001"; -- B9 WHEN "1100" => dac_d <= "10101111"; -- AF D5 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 56 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN WHEN "1011" => dac_d WHEN "1010" => dac_d WHEN "1001" => dac_d WHEN "1000" => dac_d WHEN "0111" => dac_d WHEN "0110" => dac_d WHEN "0101" => dac_d WHEN "0100" => dac_d WHEN "0011" => dac_d WHEN "0010" => dac_d WHEN "0001" => dac_d WHEN "0000" => dac_d WHEN others => dac_d END CASE; END IF; END IF; END PROCESS convert_proc; <= <= <= <= <= <= <= <= <= <= <= <= <= "10100110"; "10011100"; "10010011"; "10000000"; "01110011"; "01100110"; "01011010"; "01001101"; "01000000"; "00110100"; "00100111"; "00011010"; "10000000"; -- A6 -- 9C -- 93 -- 80 -- 73 -- 66 -- 5A -- 4D -- 40 -- 34 -- 27 -- 1A -- 80 oup_data_latch: PROCESS(sys_clk, brd_rstb, dac_d, buf_depth) BEGIN IF (brd_rstb = '0') THEN test_dout <= "10000000"; dac_dout <= "10000000"; test_depth2_0 <= "000"; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN test_dout <= dac_d; dac_dout <= dac_d; test_depth2_0 <= buf_depth(2 downto 0); END IF; END PROCESS oup_data_latch; oup_ctl: PROCESS(sys_clk, brd_rstb, nextstate) BEGIN IF (brd_rstb = '0') THEN dac_csb <= '1'; dac_wrb <= '1'; dac_abb <= '0'; test_csb <= '1'; test_wrb <= '1'; test_abb <= '0'; ELSIF (sys_clk = '1') and (sys_clk'EVENT) THEN IF (nextstate = R1 or nextstate = R3) THEN dac_csb <= '0'; test_csb <= '0'; dac_wrb <= '1'; test_wrb <= '1'; IF line_code = "00000" THEN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 57 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN dac_abb <= '0'; test_abb <= '0'; ELSE dac_abb <= '1'; test_abb <= '1'; END IF; ELSIF (line_code = "00000" and (nextstate = R2 )) THEN dac_csb <= '0'; dac_wrb <= '0'; test_csb <= '0'; test_wrb <= '0'; dac_abb <= '0'; test_abb <= '0'; ELSIF (line_code /= "00000" and (nextstate = R2 )) THEN dac_csb <= '0'; dac_wrb <= '0'; test_csb <= '0'; test_wrb <= '0'; dac_abb <= '1'; test_abb <= '1'; ELSE dac_csb <= '1'; dac_wrb <= '1'; dac_abb <= '0'; test_csb <= '1'; test_wrb <= '1'; test_abb <= '0'; END IF; END IF; END PROCESS oup_ctl; END; PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 58 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 59 RELEASED REFERENCE DESIGN PMC-1990887 ISSUE 4 AAL1GATOR-32 REFERENCE DESIGN CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2001 PMC-Sierra, Inc. PMC-1990887 (R4) Issue date: October 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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